Logic Circuits
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2022 ◽  
Vol 35 (2) ◽  
pp. 025017
Author(s):  
Quentin Herr ◽  
Alex Braun ◽  
Andrew Brownfield ◽  
Ed Rudman ◽  
Dan Dosch ◽  
...  

Abstract A circuit-simulation-based method is used to determine the thermally-induced bit error rate of superconducting Single Flux Quantum logic circuits. Simulations are used to evaluate the multidimensional Gaussian integral across noise current sources attached to the active devices. The method is data-assisted and has predictive power. Measurement determines the value of a single parameter, effective noise bandwidth, for each error mechanism. The errors in the distributed networks of comparator-free Reciprocal Quantum Logic nucleate across multiple Josephson junctions, so the effective critical current is about three times that of the individual devices. The effective noise bandwidth is only 6%–23% of the junction plasma frequency at a modest clock rate of 3.4 GHz, which is 1% of the plasma frequency. This analysis shows the ways measured bit error rate comes out so much lower than simplistic estimates based on isolated devices.


Author(s):  
Hai Li ◽  
Dmitri E. Nikonov ◽  
Chia-Ching Lin ◽  
Kerem Camsari ◽  
Yu-Ching Liao ◽  
...  
Keyword(s):  

2022 ◽  
Vol 2161 (1) ◽  
pp. 012050
Author(s):  
Imran Ahmed Khan

Abstract Due to physical, material, technological, power-thermal and economical difficulties, scaling of CMOS transistors will stop very soon. Due to efficiency of power and speed compared to CMOS transistors, Carbon Nano-tube transistors are best suitable element to design logic circuits. So, CNTFETS have been utilized in designing of proposed full adder (FA) and 4-bit ripple carry adder (RCA) in this paper. Proposed FA and RCA have been compared to rival designs on bases of power, speed and power-delay-product (PDP). FA and RCA circuits have been analysed with the variation of temperature from 0°C to 100°C while the variation of supply voltages is from 0.7V to 1.3V. For all temperatures and all supply voltages, proposed FA and proposed RCA have the least power consumption, shortest delay and lowest PDP. SPICE has been utilized for simulating FAs and RCAs in 32 nm process node. Even though the fabrication is complicated than CMOS counterparts but simulation results confirm usefulness of proposed FA and RCA for high speed and power efficient arithmetic applications.


2021 ◽  
Author(s):  
Jing Wang ◽  
Jing Ma ◽  
Houbing Huang ◽  
Ji Ma ◽  
Hasnain Jafri ◽  
...  

Abstract The electronic conductivities of ferroelectric domain walls have been extensively explored over the past decade for potential nanoelectronic applications. However, the realization of logic devices based on ferroelectric domain walls requires reliable and flexible control of the domain-wall configuration and conduction path. Here, we demonstrate electric-field-controlled stable and repeatable on-and-off switching of conductive domain walls within topologically confined vertex domains naturally formed in self-assembled ferroelectric nano-islands. Using a combination of piezoresponse force microscopy, conductive atomic force microscopy, and phase-field simulations, we show that on-off switching is accomplished through reversible transformations between charged and neutral domain walls via electric-field-controlled domain-wall reconfiguration. By analogy to logic processing, we propose programmable logic gates (such as NOT, OR, AND and their derivatives) and logic circuits (such as fan-out) based on reconfigurable conductive domain walls. Our work provides a potentially viable platform for programmable all-electric logic based on a ferroelectric domain-wall network with low energy consumption.


RSC Advances ◽  
2022 ◽  
Vol 12 (1) ◽  
pp. 338-345
Author(s):  
Cuicui Xing ◽  
Xuedong Zheng ◽  
Qiang Zhang

Preemptor blocks the strand displacement reaction by acting on DNA complex, not by directly hybridizing with the worker.


Author(s):  
Liqiang Guo ◽  
Guifa Zhang ◽  
Hui Han ◽  
Yongbin Hu ◽  
Guanggui Cheng

Abstract In recent years, low power electronic devices have attracted more and more interests. Here, flexible thin-film transistors(TFTs) with In-Ga-Zn-O (IGZO) as semiconductor channel material were fabricated on polyethylene terephthalate (PET) substrates. The device exhibits good electrical properties at low operating voltage, including high on/off ratio of ~ 7.8 × 106 and high electron mobility of ~ 23.1 cm2V-1s-1. The device also has excellent response characteristics to visible light. With the increase of visible light intensity, the threshold voltage of IGZO TFTs decreases continuously, but the electron mobility increases gradually. Based on the unique response ability of the device to light, we proposed and demonstrated that a single thin-film transistor can realize different logic operations under the light/electricity mixed modulation, including “AND” and “OR”. In addition, we also simulated some basic artificial synaptic behaviors, including excitatory postsynaptic current and paired-pulse facilitation. Thus, IGZO TFTs operating at low voltages not only have the potential to construct multifunctional optoelectronic devices, but also provide a new idea for simplifying the design of programmable logic circuits.


Author(s):  
Yasuhiro Ogasahara ◽  
Kazunori Kuribara ◽  
Kunihiro Oshima ◽  
Zhaoxing Qin ◽  
Takashi Sato

Abstract This paper reports on a strategy for yield improvement and static leakage current reduction by using a standard cell design for large-scale organic thin-film transistor (OTFT) circuits. Printable or flexible devices are suitable for IoT nodes, and digital OTFT circuits comprise the peripheral circuits of such devices. Sufficiently high yields and low static power consumptions are essential for battery operations of IoT nodes having functional digital circuits. Our design method to address the weak n-type OTFT on-current results in improved logic gate yields without any cell area increase. We improved the yield of the inverter, NAND, and NOR gates using a standard cell design, and achieved a 100%yield for the inverter and NOR gates and 88%yield for the NAND gates. Signal propagations with rail-to-rail operation were measured on test chips. Leakage currents of 585 pA and 2.94 nA were achieved for the inverter and NOR gates, respectively.


2021 ◽  
Vol 31 (16) ◽  
Author(s):  
Xiaoyuan Wang ◽  
Pu Li ◽  
Chenxi Jin ◽  
Zhekang Dong ◽  
Herbert H. C. Iu

This paper presents a general modeling method for threshold-type multivalued memristors. Through this memristor modeling method, it is very simple to establish threshold-type memristor behavior models with different numbers of memristance elements, and these models are verified by numerical MATLAB simulations. A corresponding circuit-level SPICE model of the ternary memristor behavior model is developed and simulated in LTspice, shown to be consistent with the MATLAB results. Finally, the SPICE model is used to design the AND gate, OR gate, and three NOT gates of ternary state-based logic, and the effectiveness of the circuit is proved by LTSpice simulation.


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