The Formal Design Models of Digraph Architectures and Behaviors

2012 ◽  
Vol 4 (1) ◽  
pp. 100-129 ◽  
Author(s):  
Yingxu Wang ◽  
Aderemi Adewumi
Keyword(s):  
Real Time ◽  
Code Generation ◽  
Graph Model ◽  
Hierarchical Structures ◽  
Process Models ◽  
Behavioral Models ◽  
Complicated Form ◽  
Architectural Models ◽  
Automatic Code ◽  
Formal Design

Graphs are one of the most fundamental and widely used non-linear hierarchical structures of linked nodes. Problems in sciences and engineering can be formulated and solved by the graph model. This paper develops a comprehensive design pattern of formal digraphs using the Doubly-Linked List (DLL) architecture. The most complicated form of graphs known as the weighted digraph is selected as a general graph model, based on it simple graphs such as nondirected and/or nonweighted ones can be easily derived and tailored. A rigorous denotational mathematics, Real-Time Process Algebra (RTPA), is adopted, which allows both architectural and behavioral models of digraphs to be rigorously designed and implemented in a top-down approach. The architectural models of digraphs are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The physical model of digraphs is implemented using nodes of DLL dynamically created in the memory. The behavioral models of digraphs are specified and refined by a set of 18 Unified Process Models (UPMs) in three categories namely the management operations, traversal operations, and node manipulation operations. This work has been applied in a number of real-time and nonreal-time system designs and specifications such as a Real-Time Operating System (RTOS+), graph-based and tree-based applications, and the ADT library for an RTPA-based automatic code generation tool.

The Formal Design Models of a Universal Array (UA) and its Implementation

2011 ◽  
Vol 3 (3) ◽  
pp. 69-89 ◽  
Author(s):  
Yingxu Wang ◽  
Jason Huang ◽  
Jingsheng Lei
Keyword(s):  
Real Time ◽  
Code Generation ◽  
Formal Model ◽  
Process Models ◽  
Behavioral Models ◽  
Universal Array ◽  
Linear List ◽  
Data Objects ◽  
Automatic Code ◽  
Formal Design

Arrays are one of the most fundamental and widely applied data structures, which are useful for modeling both logical designs and physical implementations of multi-dimensional data objects sharing the same type of homogeneous elements. However, there is a lack of a formal model of the universal array based on it any array instance can be derived. This paper studies the fundamental properties of Universal Array (UA) and presents a comprehensive design pattern. A denotational mathematics, Real-Time Process Algebra (RTPA), allows both architectural and behavioral models of UA to be rigorously designed and refined in a top-down approach. The conceptual model of UA is rigorously described by tuple- and matrix-based mathematical models. The architectural models of UA are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The physical model of UA is implemented using linear list that is indexed by an offset pointer of elements. The behavioral models of UA are specified and refined by a set of Unified Process Models (UPMs). As a case study, the formal UA models are implemented in Java. This work has been applied in a number of real-time and nonreal-time systems such as compilers, a file management system, the real-time operating system (RTOS+), and the ADT library for an RTPA-based automatic code generation tool.

The Formal Design Models of a Universal Array (UA) and its Implementation

2013 ◽  
pp. 241-259
Author(s):  
Yingxu Wang ◽  
Jason Huang ◽  
Jingsheng Lei
Keyword(s):  
Real Time ◽  
Code Generation ◽  
Formal Model ◽  
Process Models ◽  
Behavioral Models ◽  
Universal Array ◽  
Linear List ◽  
Data Objects ◽  
Automatic Code ◽  
Formal Design

Arrays are one of the most fundamental and widely applied data structures, which are useful for modeling both logical designs and physical implementations of multi-dimensional data objects sharing the same type of homogeneous elements. However, there is a lack of a formal model of the universal array based on it any array instance can be derived. This paper studies the fundamental properties of Universal Array (UA) and presents a comprehensive design pattern. A denotational mathematics, Real-Time Process Algebra (RTPA), allows both architectural and behavioral models of UA to be rigorously designed and refined in a top-down approach. The conceptual model of UA is rigorously described by tuple- and matrix-based mathematical models. The architectural models of UA are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The physical model of UA is implemented using linear list that is indexed by an offset pointer of elements. The behavioral models of UA are specified and refined by a set of Unified Process Models (UPMs). As a case study, the formal UA models are implemented in Java. This work has been applied in a number of real-time and nonreal-time systems such as compilers, a file management system, the real-time operating system (RTOS+), and the ADT library for an RTPA-based automatic code generation tool.

The Formal Design Model of Doubly-Linked-Circular Lists (DLC-Lists)

2013 ◽  
pp. 214-230
Author(s):  
Yingxu Wang ◽  
Cyprian F. Ngolah ◽  
Xinming Tan ◽  
Phillip C.Y. Sheu
Keyword(s):  
Real Time ◽  
Code Generation ◽  
System Modeling ◽  
Finite Sequence ◽  
Process Models ◽  
Behavioral Models ◽  
Data Types ◽  
Abstract Data ◽  
Automatic Code ◽  
Formal Design

Abstract Data Types (ADTs) are a set of highly generic and rigorously modeled data structures in type theory. Lists as a finite sequence of elements are one of the most fundamental and widely used ADTs in system modeling, which provide a standard encapsulation and access interface for manipulating large-volume information and persistent data. This paper develops a comprehensive design pattern of formal lists using a doubly-linked-circular (DLC) list architecture. A rigorous denotational mathematics, Real-Time Process Algebra (RTPA), is adopted, which allows both architectural and behavioral models of lists to be rigorously designed and implemented in a top-down approach. The architectural models of DLC-Lists are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The behavioral models of DLC-Lists are specified and refined by a set of Unified Process Models (UPMs) in three categories namely the management operations, traversal operations, and node I/O operations. This work has been applied in a number of real-time and nonreal-time system designs such as a real-time operating system (RTOS+), a file management system (FMS), and the ADT library for an RTPA-based automatic code generation tool.

The Formal Design Model of Doubly-Linked-Circular Lists (DLC-Lists)

2011 ◽  
Vol 3 (2) ◽  
pp. 83-102 ◽  
Author(s):  
Yingxu Wang ◽  
Cyprian F. Ngolah ◽  
Xinming Tan ◽  
Phillip C.Y. Sheu
Keyword(s):  
Real Time ◽  
Code Generation ◽  
System Modeling ◽  
Finite Sequence ◽  
Process Models ◽  
Behavioral Models ◽  
Data Types ◽  
Persistent Data ◽  
Automatic Code ◽  
Formal Design

Abstract Data Types (ADTs) are a set of highly generic and rigorously modeled data structures in type theory. Lists as a finite sequence of elements are one of the most fundamental and widely used ADTs in system modeling, which provide a standard encapsulation and access interface for manipulating large-volume information and persistent data. This paper develops a comprehensive design pattern of formal lists using a doubly-linked-circular (DLC) list architecture. A rigorous denotational mathematics, Real-Time Process Algebra (RTPA), is adopted, which allows both architectural and behavioral models of lists to be rigorously designed and implemented in a top-down approach. The architectural models of DLC-Lists are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The behavioral models of DLC-Lists are specified and refined by a set of Unified Process Models (UPMs) in three categories namely the management operations, traversal operations, and node I/O operations. This work has been applied in a number of real-time and nonreal-time system designs such as a real-time operating system (RTOS+), a file management system (FMS), and the ADT library for an RTPA-based automatic code generation tool.

The Formal Design Models of Tree Architectures and Behaviors

2011 ◽  
Vol 3 (4) ◽  
pp. 84-108 ◽  
Author(s):  
Yingxu Wang ◽  
Xinming Tan
Keyword(s):  
Real Time ◽  
Hierarchical Structures ◽  
General System ◽  
Process Models ◽  
Behavioral Models ◽  
Code Generator ◽  
Organization Model ◽  
B Trees ◽  
Left And Right ◽  
Automatic Code

Trees are one of the most fundamental and widely used non-linear hierarchical structures of linked nodes. A binary tree (B-Tree) is a typical balanced tree where the fan-out of each node is at most two known as the left and right children. This paper develops a comprehensive design pattern of formal trees using the B-Tree architecture. A rigorous denotational mathematics, Real-Time Process Algebra (RTPA), is adopted, which allows both architectural and behavioral models of B-Trees to be rigorously designed and implemented in a top-down approach. The architectural models of B-Trees are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The physical model of B-Trees is implemented using the left and right child nodes dynamically created in memory. The behavioral models of B-Trees are specified and refined by a set of Unified Process Models (UPMs) in three categories namely the management operations, traversal operations, and node I/O operations. This work has been applied in a number of real-time and nonreal-time system designs such as a real-time operating system (RTOS+), a general system organization model, and the ADT library for an RTPA-based automatic code generator.

The Formal Design Models of Tree Architectures and Behaviors

2013 ◽  
pp. 260-281
Author(s):  
Yingxu Wang ◽  
Xinming Tan
Keyword(s):  
Real Time ◽  
Hierarchical Structures ◽  
Process Models ◽  
Behavioral Models ◽  
Code Generator ◽  
Organization Model ◽  
B Trees ◽  
Left And Right ◽  
Balanced Tree ◽  
Automatic Code

Trees are one of the most fundamental and widely used non-linear hierarchical structures of linked nodes. A binary tree (B-Tree) is a typical balanced tree where the fan-out of each node is at most two known as the left and right children. This paper develops a comprehensive design pattern of formal trees using the B-Tree architecture. A rigorous denotational mathematics, Real-Time Process Algebra (RTPA), is adopted, which allows both architectural and behavioral models of B-Trees to be rigorously designed and implemented in a top-down approach. The architectural models of B-Trees are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The physical model of B-Trees is implemented using the left and right child nodes dynamically created in memory. The behavioral models of B-Trees are specified and refined by a set of Unified Process Models (UPMs) in three categories namely the management operations, traversal operations, and node I/O operations. This work has been applied in a number of real-time and nonreal-time system designs such as a real-time operating system (RTOS+), a general system organization model, and the ADT library for an RTPA-based automatic code generator.

The Formal Design Model of a Real-Time Operating System (RTOS+)

2012 ◽  
pp. 219-235
Author(s):  
Yingxu Wang ◽  
Cyprian F. Ngolah ◽  
Guangping Zeng ◽  
Phillip C.-Y. Sheu ◽  
C. Philip Choy ◽  
...  
Keyword(s):  
Operating System ◽  
Real Time ◽  
Process Models ◽  
Design Model ◽  
Time Process ◽  
Critical Systems ◽  
Behavioral Models ◽  
Dynamic Behaviors ◽  
Real Time Operating System ◽  
Formal Design

A real-time operating system (RTOS) provides a platform for the design and implementation of a wide range of applications in real-time systems, embedded systems, and mission-critical systems. This paper presents a formal design model for a general RTOS known as RTOS+ that enables a specific target RTOS to be rigorously and efficiently derived in real-world applications. The methodology of a denotational mathematics, Real-Time Process Algebra (RTPA), is described for formally modeling and refining architectures, static behaviors, and dynamic behaviors of RTOS+. The conceptual model of the RTOS+ system is introduced as the initial requirements for the system. The architectural model of RTOS+ is created using RTPA architectural modeling methodologies and refined by a set of Unified Data Models (UDMs). The static behaviors of RTOS+ are specified and refined by a set of Unified Process Models (UPMs). The dynamic behaviors of the RTOS+ system are specified and refined by the real-time process scheduler and system dispatcher. This work is presented in two papers; the conceptual and architectural models of RTOS+ is described in this paper, while the static and dynamic behavioral models of RTOS+ will be elaborated in a forthcoming paper.

The Formal Design Model of a Real-Time Operating System (RTOS+)

2012 ◽  
pp. 236-262
Author(s):  
Yingxu Wang ◽  
Guangping Zeng ◽  
Cyprian F. Ngolah ◽  
Phillip C.-Y. Sheu ◽  
C. Philip Choy ◽  
...  
Keyword(s):  
Operating System ◽  
Real Time ◽  
Process Models ◽  
Design Model ◽  
Time Process ◽  
Critical Systems ◽  
Behavioral Models ◽  
Dynamic Behaviors ◽  
Real Time Operating System ◽  
Formal Design

A real-time operating system (RTOS) provides a platform for the design and implementation of a wide range of applications in real-time systems, embedded systems, and mission-critical systems. This paper presents a formal design model for a general RTOS known as RTOS+ that enables a specific target RTOS to be rigorously and efficiently derived in real-world applications. The methodology of a denotational mathematics, Real-Time Process Algebra (RTPA), is described for formally modeling and refining architectures, static behaviors, and dynamic behaviors of RTOS+. The conceptual model of the RTOS+ system is introduced as the initial requirements for the system. The architectural model of RTOS+ is created using RTPA architectural modeling methodologies and refined by a set of Unified Data Models (UDMs). The static behaviors of RTOS+ are specified and refined by a set of Unified Process Models (UPMs). The dynamic behaviors of the RTOS+ system are specified and refined by the real-time process scheduler and system dispatcher. This work is presented in two papers in serial due to its excessive length. The static and dynamic behavioral models of RTOS+ is described in this paper; while the conceptual and architectural models of RTOS+ has been published in IJSSCI 2(2).

The Formal Design Model of a File Management System (FMS)

2013 ◽  
pp. 193-213
Author(s):  
Yingxu Wang ◽  
Cyprian F. Ngolah ◽  
Xinming Tan ◽  
Yousheng Tian ◽  
Phillip C.Y. Sheu
Keyword(s):  
Real Time ◽  
Management System ◽  
Data File ◽  
Abstract Data Type ◽  
Behavioral Models ◽  
Software Modeling ◽  
File Management ◽  
Abstract Data ◽  
Data Objects ◽  
Formal Design

Files are a typical abstract data type for data objects and software modeling, which provides a standard encapsulation and access interface for manipulating large-volume information and persistent data. File management systems are an indispensable component of operating systems and real-time systems for file manipulations. This paper develops a comprehensive design pattern of files and a File Management System (FMS). A rigorous denotational mathematics, Real-Time Process Algebra (RTPA), is adopted, which allows both architectural and behavioral models of files and FMS to be rigorously designed and implemented in a top-down approach. The conceptual model, architectural model, and the static/dynamic behavioral models of files and FMS are systematically presented. This work has been applied in the design and modeling of a real-time operating system (RTOS+).

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