Design and Implementation of Unified DCT/IDCT Architecture Based on FPGA

2014 ◽  
Vol 981 ◽  
pp. 323-326
Author(s):  
Hai Huang ◽  
Jia Ming Liu ◽  
Xue Bin Lu ◽  
Bin Yu

This paper proposes a unified architecture for computation of discrete cosine transform (DCT) and its inverse transform (IDCT). The matrix decomposition algorithm is used to deduce the proposed algorithm. Based on this algorithm, a unified DCT/IDCT architecture is developed. Then, this architecture is modeled in HDL, verified and implemented with FPGA. Experiment results show that the unified DCT/IDCT architecture has low hardware complexity and high calculation accuracy.

Author(s):  
DANESHWARI I. HATTI ◽  
SAVITRI RAJU ◽  
MAHENDRA M. DIXIT

In digital communication bandwidth is essential parameter to be considered. Transmission and storage of images requires lot of memory in order to use bandwidth efficiently neural network and Discrete cosine transform together are used in this paper to compress images. Artificial neural network gives fixed compression ratio for any images results in fixed usage of memory and bandwidth. In this paper multi-layer feedforward neural network has been employed to achieve image compression. The proposed technique divides the original image in to several blocks and applies Discrete Cosine Transform (DCT) to these blocks as a pre-process technique. Quality of image is noticed with change in training algorithms, convergence time to attain desired mean square error. Compression ratio and PSNR in dB is calculated by varying hidden neurons. The proposed work is designed using MATLAB 7.10. and synthesized by mapping on Vertex 5 in Xilinx ISE for understanding hardware complexity. Keywords - backpropagation, Discrete


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