FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm

2011 ◽  
Vol 6 (1) ◽  
Author(s):  
Vikram Arkalgud Chandrasetty ◽  
Syed Mahfuzul Aziz
Author(s):  
Tarigan Aditia ◽  
Rita Purnamasari ◽  
Efa Maydhona Saputra

LDPC is one of channel coding technique which can achieve the nearest to the shannon limit. The focus of this paper is to give improvement for LDPC error correcting process using message passing algorithm. This works used FPGA Cyclon II for implementing the process. This paper worked with two different LDPC matrix, matrix (8, 16) and matrix (24, 48). Matrix (24,48) had wc = 4 and wr = 8. Matrix (8, 16) had wc = 2 and wr = 4. The comparison of these two matrix would present the effects in the error correcting decision for message passing algorithm and the effect for implementing the algorithm on FPGA Cyclon II. This research purpose was to prove message passing algorithm can provide more than one bit error correction.


2016 ◽  
Vol 23 (6) ◽  
pp. 828-832 ◽  
Author(s):  
Burak Cakmak ◽  
Daniel N. Urup ◽  
Florian Meyer ◽  
Troels Pedersen ◽  
Bernard H. Fleury ◽  
...  

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