Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision

Low-density parity-check (LDPC) codes have been widely adopted in NAND flash in recent years to enhance data reliability. There are two types of decoding, hard-decision and soft-decision decoding. However, for the two types, their error correction capability degrades due to inaccurate log-likelihood ratio (LLR) . To improve the LLR accuracy of LDPC decoding, this article proposes LLR optimization schemes, which can be utilized for both hard-decision and soft-decision decoding. First, we build a threshold voltage distribution model for 3D floating gate (FG) triple level cell (TLC) NAND flash. Then, by exploiting the model, we introduce a scheme to quantize LLR during hard-decision and soft-decision decoding. And by amplifying a portion of small LLRs, which is essential in the layer min-sum decoder, more precise LLR can be obtained. For hard-decision decoding, the proposed new modes can significantly improve the decoder’s error correction capability compared with traditional solutions. Soft-decision decoding starts when hard-decision decoding fails. For this part, we study the influence of the reference voltage arrangement of LLR calculation and apply the quantization scheme. The simulation shows that the proposed approach can reduce frame error rate (FER) for several orders of magnitude.

Efficient Iterative Timing Recovery of Low-Density Parity-Check Decoding Metrics Using the Steepest Descent Algorithm for Satellite Communications at Low SNRs

An efficient iterative timing recovery via steepest descent of low-density parity-check (LDPC) decoding metrics is presented. In the proposed algorithm, a more accurate symbol timing synchronization is achieved at a low signal-to-noise (SNR) without any pilot symbol by maximizing the sum of the square of all soft metrics in LDPC decoding. The principle of the above-proposed algorithm is analyzed theoretically with the evolution trend of the probability mean of the soft LDPC decoding metrics by the Gaussian approximation. In addition, an efficiently approximate gradient descent algorithm is adopted to obtain excellent timing recovery with rather low complexity and global convergence. Finally, a complete timing recovery is accomplished where the proposed scheme performs fine timing capture, followed by a traditional Mueller–Müller (M&M) timing recovery, which acquires timing track. Using the proposed iterative timing recovery method, the simulation results indicate that the performance of the LDPC coded binary phase shift keying (BPSK) scheme with rather large timing errors is just within 0.1 dB of the ideal code performance at the cost of some rational computation and storage. Therefore, the proposed iterative timing recovery can be efficiently applied on occasions of the weak signal timing synchronization in satellite communications and so on.

Enhancing Performance of Lossy Compression on Encrypted Gray Images through Heuristic Optimization of Bitplane Allocation

Nowadays, it remains a major challenge to efficiently compress encrypted images. In this paper, we propose a novel encryption-then-compression (ETC) scheme to enhance the performance of lossy compression on encrypted gray images through heuristic optimization of bitplane allocation. Specifically, in compressing an encrypted image, we take a bitplane as a basic compression unit and formulate the lossy compression task as an optimization problem that maximizes the peak signal-to-noise ratio (PSNR) subject to a given compression ratio. We then develop a heuristic strategy of bitplane allocation to approximately solve this optimization problem, which leverages the asymmetric characteristics of different bitplanes. In particular, an encrypted image is divided into four sub-images. Among them, one sub-image is reserved, while the most significant bitplanes (MSBs) of the other sub-images are selected successively, and so are the second, third, etc., MSBs until a given compression ratio is met. As there exist clear statistical correlations within a bitplane and between adjacent bitplanes, where bitplane denotes those belonging to the first three MSBs, we further use the low-density parity-check (LDPC) code to compress these bitplanes according to the ETC framework. In reconstructing the original image, we first deploy the joint LDPC decoding, decryption, and Markov random field (MRF) exploitation to recover the chosen bitplanes belonging to the first three MSBs in a lossless way, and then apply content-adaptive interpolation to further obtain missing bitplanes and thus discarded pixels, which is symmetric to the encrypted image compression process. Experimental simulation results show that the proposed scheme achieves desirable visual quality of reconstructed images and remarkably outperforms the state-of-the-art ETC methods, which indicates the feasibility and effectiveness of the proposed scheme.

FPGA implementation of LDPC soft-decision decoders based DCSK for spread spectrum applications

<span lang="EN-US">Spread spectrum (SS) communications have attracted interest because of their channel attenuation immunity and low intercept potential. Apart from some extra features such as basic transceiver structures, chaotic communication would be the analog alternative to digital SS systems. Differential chaos shift keying (DCSK) systems, non-periodic and random characteristics among chaos carriers as well as their interaction with soft data are designed based on low-density parity-check (LDPC) codes in this brief. Because of simple structure, and glorious ability to <span>correct errors. Using the Xilinx kintex7 FPGA development kit, we investigate the hardware performance and resource requirement tendencies of the DCSK</span> communication system based on LDPC decoding algorithms (Prob. Domain, Log Domain and Min-Sum) over AWGN channel. The results indicate that the proposed system model has substantial improvements in the performance of the bit error rate (BER) and the real-time process. The Min-Sum decoder has relatively fewer FPGA resources than the other decoders. The implemented system will achieve 10-4 BER efficiency with 5 dB associate E_b/N_o as a coding gain.</span>

An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder

<span lang="EN-US">For low density parity check (LDPC) decoding, hard-decision algorithms are sometimes more suitable than the soft-decision ones. Particularly in the high throughput and high speed applications. However, there exists a considerable gap in performances between these two classes of algorithms in favor of soft-decision algorithms. In order to reduce this gap, in this work we introduce two new improved versions of the hard-decision algorithms, the adaptative gradient descent bit-flipping (AGDBF) and adaptative reliability ratio weighted GDBF (ARRWGDBF). An adaptative weighting and correction factor is introduced in each case to improve the performances of the two algorithms allowing an important gain of bit error rate. As a second contribution of this work a real time implementation of the proposed solutions on a digital signal processors (DSP) is performed in order to optimize and improve the performance of these new approchs. The results of numerical simulations and DSP implementation reveal a faster convergence with a low processing time and a reduction in consumed memory resources when compared to soft-decision algorithms. For the irregular LDPC code, our approachs achieves gains of 0.25 and 0.15 dB respectively for the AGDBF and ARRWGDBF algorithms.</span>