scholarly journals Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems

2014 ◽  
Author(s):  
Manil Dev Gomony ◽  
Benny Akesson ◽  
Kees Goossens
Keyword(s):  
Real Time ◽  
Performance Optimization ◽  
Real Time Systems ◽  
And Performance ◽  
Time Systems

scholarly journals Reliability and performance optimization of pipelined real-time systems

2013 ◽  
Vol 73 (6) ◽  
pp. 851-865 ◽  
Author(s):  
Anne Benoit ◽  
Fanny Dufossé ◽  
Alain Girault ◽  
Yves Robert
Keyword(s):  
Real Time ◽  
Performance Optimization ◽  
Real Time Systems ◽  
And Performance ◽  
Time Systems

scholarly journals Online On-the-Fly Testing of Real-time Systems

2003 ◽  
Vol 10 (49) ◽  
Author(s):  
Marius Mikucionis ◽  
Kim G. Larsen ◽  
Brian Nielsen
Keyword(s):  
Real Time ◽  
Test Generation ◽  
Timed Automata ◽  
Online Testing ◽  
Real Time Systems ◽  
Model Checker ◽  
Test Specification ◽  
And Performance ◽  
Automata Network ◽  
Time Systems

In this paper we present a framework, an algorithm and a new tool for online testing of real-time systems based on symbolic techniques used in UPPAAL model checker. We extend UPPAAL timed automata network model to a test specification which is used to generate test primitives and to check the correctness of system responses including the timing aspects. We use timed trace inclusion as a conformance relation between system and specification to draw a test verdict. The test generation and execution algorithm is implemented as an extension to UPPAAL and experiments carried out to examine the correctness and performance of the tool. The experiment results are promising.

Formal Analysis of Real-Time Systems

2011 ◽  
pp. 342-375
Author(s):  
Osman Hasan ◽  
Sofiène Tahar
Keyword(s):  
Performance Analysis ◽  
Real Time ◽  
Formal Analysis ◽  
Higher Order ◽  
Order Logic ◽  
Real Time Systems ◽  
Higher Order Logic ◽  
Distributed Components ◽  
And Performance ◽  
Time Systems

Real-time systems usually involve a subtle interaction of a number of distributed components and have a high degree of parallelism, which makes their performance analysis quite complex. Thus, traditional techniques, such as simulation, or state-based formal methods usually fail to produce reasonable results. The main limitation of these approaches may be overcome by conducting the performance analysis of real-time systems using higher-order-logic theorem proving. This chapter is mainly oriented towards this emerging trend and it provides the details about analyzing both functional and performance related properties of real-time systems using a higher-order-logic theorem prover (HOL). For illustration purposes, the Stop-and-Wait protocol, which is a classical example of real-time systems, has been considered as a case-study.

scholarly journals On Self-Timed Circuits in Real-Time Systems

2011 ◽  
Vol 2011 ◽  
pp. 1-16 ◽  
Author(s):  
Markus Ferringer
Keyword(s):  
Real Time ◽  
Supply Voltage ◽  
Real Time Systems ◽  
Asynchronous Logic ◽  
Timing Model ◽  
Execution Speed ◽  
Timed Circuits ◽  
And Performance ◽  
Suitable Notion ◽  
Time Systems

While asynchronous logic has many potential advantages compared to traditional synchronous designs, one of the major drawbacks is its unpredictability with respect to temporal behavior. Having no high-precision oscillator, a self-timed circuit's execution speed is heavily dependent on temperature and supply voltage. Small fluctuations of these parameters already result in noticeable changes of the design's throughput and performance. Without further provisions this jitter makes the use of asynchronous logic hardly feasible for real-time applications. We investigate the temporal characteristics of self-timed circuits regarding their usage in real-time systems, especially the Time-Triggered Protocol. We propose a simple timing model and elaborate a self-adapting circuit which shall derive a suitable notion of time for both bit transmission and protocol execution. We further introduce and analyze our jitter compensation concept, which is a threefold mechanism to keep the asynchronous circuit's notion of time tightly synchronized to the remaining communication participants. To demonstrate the robustness of our solution, we perform different tests and investigate their impact on jitter and frequency stability.

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