Petri Net Based Deadlock Prevention Approach for Flexible Manufacturing Systems

In flexible manufacturing systems, deadlocks usually occur due to the limited resources. To cope with deadlock problems, Petri nets are widely used to model these systems. This chapter focuses on deadlock prevention for flexible manufacturing systems that are modeled with S4R nets, a subclass of generalized Petri nets. The analysis of S4R leads us to derive an iterative deadlock prevention approach. At each iteration step, a non-max-controlled siphon is derived by solving a mixed integer linear programming. A monitor is constructed for the siphon such that it is max-controlled. Finally, a liveness-enforcing Petri net supervisor can be derived without enumerating all the strict minimal siphons.

Reconfigurable Embedded Control Systems

The chapter deals with distributed multi-agent reconfigurable embedded control systems following the component-based International Industrial Standard IEC61499 in which a Function Block (abbreviated by FB) is an event-triggered software component owning data and a control application is a distributed network of Function Blocks that have classically to satisfy functional and to meet temporal properties described in user requirements. The authors define a new reconfiguration semantic where a crucial criterion to consider is the automatic improvement of the system’s performance at run-time, in addition to its protection when hardware faults occur. To handle all possible cases in industry, the authors classify thereafter the reconfiguration scenarios into three forms before the authors define an architecture of reconfigurable multi-agent systems where a Reconfiguration Agent is affected to each device of the execution environment to apply local reconfigurations, and a Coordination Agent is proposed for any coordination between devices in order to guarantee safe and adequate distributed reconfigurations. A Communication Protocol is proposed in our research work to handle coordinations between agents by using well-defined Coordination Matrices. The authors specify both the reconfiguration agents to be modelled by nested state machines, and the Coordination Agent according to the formalism Net Condition/Event Systems (Abbreviated by NCES) which is an extension of Petri nets. To verify the whole architecture, the author check by applying the model checker SESA in each device functional and temporal properties described in the temporal logic “Computation Tree Logic”, but the authors have also to check any coordination between devices by verifying that whenever a reconfiguration is applied in a device, the Coordination Agent and other concerned devices should react as described in user requirements. The chapter’s contributions are applied to two Benchmark Production Systems available in our research laboratory.

Multithreaded Programming of Reconfigurable Embedded Systems

Embedded and Real-Time (ERTS) systems have continued to expand at a vigorous rate. Designers of ERTS systems are continually challenged to provide new capabilities that can meet the expanding requirements and increased computational needs of each new proposed application, but at a decreasing price/performance ratio. Conventional solutions using general purpose processors or custom ASICs are less and less able to satisfy the contradictory requirements in performance, flexibility, power, development time, and cost. This chapter introduces the concept of generating semi-custom platforms driven from a traditional multithreaded programming model. This approach offers the advantage of achieving productivity levels close to those associated with software by using an established programming model but with a performance level close to custom hardware through the use of a flexible hardware platform capable of adapting to specialized application requirements. We discuss the underlying concepts, requirements and advantages of multithreading in the context of reconfigurable hardware, and present two approaches which provide multithreading support to hardware and software components at the operating system level.

Iterative Knowledge Based Embedded Systems Development Framework

Developing an embedded software solution can be time consuming and challenging especially for non-software trained engineers. This is because traditionally, embedded software is programmed manually in proprietary computer languages such as C, C++, Java and assembly languages, meaning that the developers have to be familiar with at least one of these languages. In addition, most of the embedded software design environments do not cater for both microprocessors-based and Field Programmable Gate Array (FPGA) based embedded computing environments, making the development process even more difficult without the assistance of a common method. This chapter proposes a design of a new embedded system code generator framework which is based on the International Electrotechnical Commission (IEC) 61499 Function Block, XML and EBNF. Along with this code generator, an Iterative Knowledge Based Code Generator (IKBCG) is presented to improve the accuracy of the target codes.

A Model-Based Approach To Configure and Reconfigure Avionics Systems

Aircraft manufacturers have been moving toward the Integrated Modular Avionics (IMA) approach to reduce the number of dedicated boxes in the aircraft. Standards such as as DO178B or ARINC 653 must be followed during design, configuration or certification of IMA systems. Productivity and costs must also be improved while preserving conformance to standards. For instance, development process of avionics systems involves several system representations and representation transformations are done manually. Moreover, the complexity of new generation of safety-critical systems has also increased the complexity of their development. The authors present their component-based approach which relies on an appropriate modeling language (AADL) combined with modeling patterns to represent, configure and deploy an IMA system. It reduces costs by detecting errors earlier and prevents specifications revisions. Their code generator reduces memory footprint and improves code coverage. One last benefit is a possible automatic certification.

A Design Methodology of MIN-Based Network for MPPSoC on Reconfigurable Architecture

Massive parallel processing systems, particularly Single Instruction Multiple Data architectures, play a crucial role in the field of data intensive parallel applications. One of the primary goals in using these systems is their scalability and their linear increase in processing power by increasing the number of processing units. However, communication networks are the big challenging issue facing researchers. One of the most important networks on chip for parallel systems is the multistage interconnection network. In this paper, we propose a design methodology of multistage interconnection networks for massively parallel systems on chip. The framework covers the design step from algorithm level to RTL. We first develop a functional formalization of MIN-based on-chip network at a high level of abstraction. The specification and the validation of the model have been defined in the logic of ACL2 proving system. The main objective in this step is to provide a formal description of the network that integrates architectural parameters which have a huge impact on design costs. After validating the functional model, step 2 consists in the design and the implementation of the Delta multistage networks on chip dedicated to parallel multi-cores architectures on reconfigurable platforms FPGA. In the last step, we propose an evaluation methodology based on performance and cost metrics to evaluate different topologies of dynamic network through data parallel applications with different number of cores. We also show in the proposed framework that multistage interconnection networks are cost-effective high performance networks for parallel SOCs.

Reconfiguration of Uniprocessor Sporadic Real-Time Systems

In this chapter the authors focus on the problem of reconfiguring embedded real-time systems. Such reconfiguration can be decided either off-line to determine if a given application can be run on a different platform, while preserving the timeliness constraints imposed by the application, or on-line, where a reconfiguration should be done to adapt the system to the context of execution or to handle hardware or software faults. The task model considered in this chapter is the classical sporadic task model defined by a Worst Case Execution Time (WCET), a minimum inter-arrival time (also denoted the minimum Period) and a late termination deadline. The authors consider two preemptive scheduling strategies: Fixed Priority highest priority first (FP) and Earliest Deadline First (EDF). They propose a sensitivity analysis to handle reconfiguration issues. Sensitivity analysis aims at determining acceptable deviations from the specifications of a problem due to evolutions in system characteristics (reconfiguration or performance tuning). They present a state of the art for sensitivity analysis in the case of WCETs, Periods and Deadlines reconfigurations and study to what extent sensitivity analysis can be used to decide on the possibility of reconfiguring a system.

Zero-Downtime Reconfiguration of Distributed Control Logic in Industrial Automation and Control

Future manufacturing is envisioned to be highly flexible and adaptable. New technologies for efficient engineering of reconfigurable systems and their adaptations are preconditions for this vision. Without such solutions, engineering adaptations of Industrial Process Measurement and Control Systems (IPMCS) will exceed the costs of engineered systems by far and the reuse of equipment will become inefficient. Especially the reconfiguration of control applications is not sufficiently solved by state-of-the-art technology. This chapter gives an overview of the use of reconfiguration applications for zero-downtime system reconfiguration of control applications on basis of the standard IEC 61499 which provides a reference model for distributed and reconfigurable control systems. A new approach for the reconfiguration of IEC 61499 based control application and the corresponding modeling is discussed. This new method significantly increases engineering efficiency and reuse in component-based IPMCS.

Multi-Agent Reconfigurable Embedded Systems

The chapter deals with reconfigurable embedded control systems following component-based technologies and/or Architecture Description Languages used today in industry. The author defines Control Components as software units to support control tasks of the system which is assumed to be a network of components with precedence constraints. The author defines an agent-based architecture to handle automatic reconfigurations under well-defined conditions by creating, deleting or updating components to bring the whole system into safe and optimal behaviors. To cover all reconfiguration forms, the agent is modelled by nested state machines such that states correspond to other state machines. Several complex networks can implement the system where each one is executed at a given time when a corresponding reconfiguration scenario is automatically applied by the agent. To check the correctness of each one of them, we apply in several steps a refinement-based approach that automatically specifies feasible Control Components according to NCES. The model checker SESA is automatically applied in each step to verify deadlock properties of new generated components, and it is manually used to verify CTL-based properties according to user requirements. We implement the reconfiguration agent by three modules that allow interpretations of environment evolutions, decisions of useful reconfiguration scenarios and finally their applications. Two Industrial Benchmark Production Systems FESTO and EnAS available in the author’s research laboratory are applied to explain the paper contribution.

Specification and Validation of Real Time Systems

The chapter presents a specification technique borrowing features from two classes of specification methods, formal and semi-formal ones. Each of the above methods have been proved to be useful in the development of real-time and critical systems and widely reported in different papers (Bruel, 1996; Clarke & Wing, 1996; Cohen, 1994; Fitzgerald & Larsen, 1994; Ghezzi, Mandrioli & Morzenti, 1990). Formal methods are based on mathematical notations and axiomatic which induce verification and validation. Semi-formal methods are, in the other hand, graphic, structural and uer-friendly. Each method is applied on a suitable case study, that we regret some missing features we could find in the other class. This remark has motivated our work. We are interested in the integration of formal and semi-formal methods in order to lay out a specification approach which combines the advantages of theses two classes of methods. The proposed technique is based on the integration of the semi-formal method STATEMATE (Harel, 1997; Harel, 1987) and the temporal logic FNLOG (Sowmya & Ramesh, 1997). This choice is justified by the fact that FNLOG is formal, deals with quantitative temporal properties and that these two approaches have a compatibility which simplifies their integration (Sowmya & Ramesh, 1997). The proposed integration approach uses the notations of STATEMATE and FNLOG, defines various transformation rules of a STATEMATE specification towards FNLOG and extends the axiomatics of the temporal logic FNLOG by new lemmas to deal with duration properties. The chapter presents the various steps of our integration approach, the proposed extentions and illustrates it over a case of critical real-time systems: the gas burner system (Ravn, Rishel & Hansen, 1993).