Design and implementation of modified iterative logarithmic multiplier for low-power and area-efficient applications

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) ◽

Design and implementation of area efficient, low power AMBA-APB Bridge for SoC

10.1109/icgccee.2014.6922239 ◽

2014 ◽

Author(s):

Abhijeet Paunikar ◽

Rohan Gavankar ◽

Nachiket Umarikar ◽

K. Sivasankaran

Keyword(s):

Low Power ◽

Design and Implementation of Low-Power, Area-Efficient Fir Filter using Different Distributed Arithmetic Techniques

Indian Journal of Science and Technology ◽

10.17485/ijst/2015/v8i21/79128 ◽

2015 ◽

Vol 8 (21) ◽

Author(s):

Pilli Ramesh ◽

P. Augusta Sophy Beulet

Keyword(s):

Low Power ◽

Fir Filter ◽

Distributed Arithmetic ◽

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) ◽

Design and Implementation of Sixteen-bit Low Power and Area Efficient Dadda Multiplier

10.1109/rteict46194.2019.9016834 ◽

2019 ◽

Cited By ~ 1

Author(s):

V Manu ◽

A M Vijaya Prakash ◽

Mohan U Chandra

Keyword(s):

Low Power ◽

Design and implementation of a low power and area efficient sequential multiplier

Communication and Computing Systems ◽

10.1201/9781315364094-110 ◽

2016 ◽

Author(s):

Mohit Kumar ◽

Nitin Dhaka ◽

Rohit Toliya ◽

S Yadav

Keyword(s):

Low Power ◽

2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) ◽

Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier

10.1109/vlsid.2016.36 ◽

2016 ◽

Cited By ~ 3

Author(s):

Rahul Shrestha ◽

Utkarsh Rastogi

Keyword(s):

Low Power ◽

Booth Multiplier ◽

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

Design of an Area-Efficient and Low-Power Hierarchical NoC Architecture Based on Circuit Switching

10.1587/transfun.e92.a.890 ◽

2009 ◽

Vol E92-A (3) ◽

pp. 890-899

Author(s):

Woo Joo KIM ◽

Sung Hee LEE ◽

Sun Young HWANG

Keyword(s):

Low Power ◽

Circuit Switching ◽

Low-Power and Area-Efficient Approximate Parallel Design Using Bypassing

SSRN Electronic Journal ◽

10.2139/ssrn.3428931 ◽

2019 ◽

Cited By ~ 1

Author(s):

Anushka Prakash B ◽

Noah Kiran Nandi ◽

Marimuthu R ◽

Balamurugan S ◽

Duraivel A.N.

Keyword(s):

Low Power ◽

Parallel Design ◽

VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Recent Patents on Computer Science ◽

10.2174/2213275908666150220203501 ◽

2017 ◽

Vol 9 (3) ◽

pp. 216-221

Author(s):

Abdul Kareem ◽

Vardhana M. ◽

Praveen Kumar

Keyword(s):

Low Power ◽

High Speed ◽

Vlsi Implementation ◽

Mathematical Techniques ◽

2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID) ◽

HIPER: Low Power, High Performance and Area-Efficient Hardware Accelerators for Hidden Periodicity Detection using Ramanujan Filter Banks

10.1109/vlsid51830.2021.00024 ◽

2021 ◽

Author(s):

Arghadip Das ◽

Chandrachur Majumder ◽

Debaprasad De ◽

Arnab Raha ◽

Mrinal Kanti Naskar

Keyword(s):

Low Power ◽

High Performance ◽

Filter Banks ◽

Hardware Accelerators ◽

Periodicity Detection ◽

Design and Implementation of a Low Power Ternary Content Addressable Memory (TCAM)

2020 International SoC Design Conference (ISOCC) ◽

10.1109/isocc50952.2020.9333092 ◽

2020 ◽

Author(s):

Karthik S ◽

Karthick D ◽

Sanjaya M V ◽

Madhav Rao

Keyword(s):

Low Power ◽

Content Addressable Memory ◽

Ternary Content Addressable Memory