fpga verification Latest Research Papers

Design and FPGA Verification of Custom-Shaped Chaotic Attractors Using Rotation, Offset Boosting and Amplitude Control

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2021.3082271 ◽

2021 ◽

pp. 1-1

Author(s):

Wafaa S. Sayed ◽

Merna Roshdy ◽

Lobna A. Said ◽

Ahmed G. Radwan

Keyword(s):

Chaotic Attractors ◽

Amplitude Control ◽

Offset Boosting ◽

Fpga Verification

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Implementation of Data Automation System using SDK's Memory Map for FPGA Verification

The Journal of Korean Institute of Information Technology ◽

10.14801/jkiit.2020.18.10.133 ◽

2020 ◽

Vol 18 (10) ◽

pp. 133-138

Author(s):

Sangwook Park ◽

Bongsoon Kang

Keyword(s):

Automation System ◽

Fpga Verification

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A FPGA Verification of Improvement Edge Detection using Separation and Buffer Line

2020 International Conference on Electronics, Information, and Communication (ICEIC) ◽

10.1109/iceic49074.2020.9051159 ◽

2020 ◽

Author(s):

Tao Peng ◽

Thathupara Subramanyan Kavya ◽

Erdenetuya ◽

Young-Min Jang ◽

Sang-Bock Cho

Keyword(s):

Edge Detection ◽

Fpga Verification

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Real-time FPGA Verification for 25G-PON and 50G-PON LDPC Codes

Conference on Lasers and Electro-Optics ◽

10.1364/cleo_si.2020.sth3l.5 ◽

2020 ◽

Author(s):

Weiming Wang ◽

Kai Tao ◽

Weifeng Qian ◽

Yi Cai ◽

Ming Lei ◽

...

Keyword(s):

Real Time ◽

Ldpc Codes ◽

Fpga Verification

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FPGA Verification of Radar Signal Processing Based on SoC

2019 IEEE International Conference on Signal, Information and Data Processing (ICSIDP) ◽

10.1109/icsidp47821.2019.9172898 ◽

2019 ◽

Author(s):

XiaoYing Chen ◽

XingHua Wang ◽

Ying Liu ◽

ZiCheng Liu ◽

Jian An

Keyword(s):

Signal Processing ◽

Radar Signal ◽

Radar Signal Processing ◽

Fpga Verification

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A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties

IEEE Design and Test ◽

10.1109/mdat.2018.2890238 ◽

2019 ◽

Vol 36 (2) ◽

pp. 81-87

Author(s):

Kyuseung Han ◽

Jae-Jin Lee ◽

Woojoo Lee ◽

Jinho Lee

Keyword(s):

Network On Chip ◽

Fpga Verification ◽

On Chip ◽

Intellectual Properties

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Volatile Register Handling for FPGA Verification Based on SVAs Incorporated into UVM Environments

2019 IEEE Aerospace Conference ◽

10.1109/aero.2019.8742109 ◽

2019 ◽

Author(s):

Kai Borchers ◽

Sergio Montenegro ◽

Frank Dannemann

Keyword(s):

Fpga Verification

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A fast HDL model for full-custom FPGA verification

2017 IEEE 12th International Conference on ASIC (ASICON) ◽

10.1109/asicon.2017.8252644 ◽

2017 ◽

Cited By ~ 2

Author(s):

Kaixuan Zhang ◽

Zhihua Feng ◽

Hao Zhou

Keyword(s):

Fpga Verification

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A 3-wire SPI Protocol Chip Design with Application-Specific Integrated Circuit (ASIC) and FPGA Verification

Proceedings of the 3rd World Congress on Electrical Engineering and Computer Systems and Science ◽

10.11159/eee17.110 ◽

2017 ◽

Author(s):

Min-Chun Tuan ◽

Shih-Lun Chen ◽

Yu-Kuen Lai ◽

Chun-Chieh Chen ◽

Ho-Yin Lee

Keyword(s):

Integrated Circuit ◽

Chip Design ◽

Circuit Asic ◽

Fpga Verification ◽

Application Specific Integrated Circuit ◽

Application Specific

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Design and FPGA verification of a quasi-cyclic LDPC code for optical communication systems

2016 8th IEEE Latin-American Conference on Communications (LATINCOM) ◽

10.1109/latincom.2016.7811566 ◽

2016 ◽

Author(s):

Genaro Bergero ◽

Damian A. Morero ◽

Ariel L. Pola ◽

Mario A. Castrillon ◽

Mario R. Hueda

Keyword(s):

Optical Communication ◽

Communication Systems ◽

Ldpc Code ◽

Fpga Verification ◽

Optical Communication Systems

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fpga verification
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

Design and FPGA Verification of Custom-Shaped Chaotic Attractors Using Rotation, Offset Boosting and Amplitude Control

Implementation of Data Automation System using SDK's Memory Map for FPGA Verification

A FPGA Verification of Improvement Edge Detection using Separation and Buffer Line

Real-time FPGA Verification for 25G-PON and 50G-PON LDPC Codes

FPGA Verification of Radar Signal Processing Based on SoC

A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties

Volatile Register Handling for FPGA Verification Based on SVAs Incorporated into UVM Environments

A fast HDL model for full-custom FPGA verification

A 3-wire SPI Protocol Chip Design with Application-Specific Integrated Circuit (ASIC) and FPGA Verification

Design and FPGA verification of a quasi-cyclic LDPC code for optical communication systems

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fpga verificationRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

Design and FPGA Verification of Custom-Shaped Chaotic Attractors Using Rotation, Offset Boosting and Amplitude Control

Implementation of Data Automation System using SDK's Memory Map for FPGA Verification

A FPGA Verification of Improvement Edge Detection using Separation and Buffer Line

Real-time FPGA Verification for 25G-PON and 50G-PON LDPC Codes

FPGA Verification of Radar Signal Processing Based on SoC

A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties

Volatile Register Handling for FPGA Verification Based on SVAs Incorporated into UVM Environments

A fast HDL model for full-custom FPGA verification

A 3-wire SPI Protocol Chip Design with Application-Specific Integrated Circuit (ASIC) and FPGA Verification

Design and FPGA verification of a quasi-cyclic LDPC code for optical communication systems

fpga verification
Recently Published Documents