A Lightweight AES Coprocessor Based on RISC-V Custom Instructions

With the increasing popularity of the Internet of Things (IoT), the issue of its information security has drawn more and more attention. To overcome the resource constraint barrier for secure and reliable data transmission on the widely used IoT devices such as wireless sensor network (WSN) nodes, many researcher studies consider hardware acceleration of traditional cryptographic algorithms as one of the effective methods. Meanwhile, as one of the current research topics in the reduced instruction set computer (RISC), RISC-V provides a solid foundation for implementing domain-specific architecture (DSA). To this end, we propose an extended instruction scheme for the advanced encryption standard (AES) based on RISC-V custom instructions and present a coprocessor designed on the open-source core Hummingbird E203. The AES coprocessor uses direct memory access channels to achieve parallel data access and processing, which provides flexibility in memory space allocation and improves the efficiency of cryptographic components. Applications with embedded AES custom instructions running on an experimental prototype of the field-programmable gate array (FPGA) platform demonstrated a 25.3% to 37.9% improvement in running time over previous similar works when processing no less than 80 bytes of data. In addition, the application-specific integrated circuit (ASIC) experiments show that in most cases, the coprocessor only consumes up to 20% more power than the necessary AES operations.

The SALT—Readout ASIC for Silicon Strip Sensors of Upstream Tracker in the Upgraded LHCb Experiment

SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.

The diffraction detector for the EMD of the CSNS

On 23rd August 2018, the China Spallation Neutron Source (CSNS) located in Dongguan operated 4 neutron instruments. In the future, twenty neutron spectrometers will be built to provide multidisciplinary platforms for scientific research by national institutions, universities, and industries. Engineering Material Diffractometer (EMD), which will be used for strain measurements in engineering materials and components, will be constructed at the Beamline 8 in 2022. A novel thermal neutron detector, which will comply with the requirements of EMD application, is being developed. This detector will consist of 6LiF/ZnS(Ag) scintillation screens, wavelength shifting fiber (WLSF) arrays, a silicon photomultiplier (SiPM) and Application Specific Integrated Circuit (ASIC) read-out electronics. Each scintillation screen will be inclined with respect to the incident neutron beam at a grazing angle θ = 17°. Such geometry will not only improve the spatial resolution of detectors but also the neutron detection efficiency. The prototype of detector module has been tested at the neutron Beamline 20 at the CSNS. The experimental results obtained for this prototype illustrate that the pixel size of detector module is 3 mm and the detection efficiency exceeds 40% at the neutron wavelength of 1 Å. Based on these results, we design and manufacture the final version of the detector for the EMD application, which is characterized by low power consumption, highly integrated and easy to install. 70 such detectors will be installed till the end of 2021.

Design of a BIST implemented AES crypto-processor ASIC

This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.

Method for improving ripple reduction during phase shedding in multiphase buck converters for SCADA systems

In the current digital environment, central processing unit (CPUs), field programmable gate array (FPGAs), application-specific integrated circuit (ASICs), as well as peripherals, are growing progressively complex. On motherboards in many areas of computing, from laptops and tablets to servers and Ethernet switches, multiphase phase buck regulators are seen to be more common nowadays, because of the higher power requirements. This study describes a four-stage buck converter with a phase shedding scheme that can be used to power processors in programmable logic controller (PLCs). The proposed power supply is designed to generate a regulated voltage with minimal ripple. Because of the suggested phase shedding method, this power supply also offers better light load efficiency. For this objective, a multiphase system with phase shedding is modeled in MATLAB SIMULINK, and the findings are validated.

A Novel Transfer Function Based Ring-Down Suppression System for PMUTs

In this paper, a novel ring-down suppression system based on transfer function is proposed for the first time to suppress the ring-down time and decrease the blind area of PMUTs (Piezoelectric Micromachined Ultrasonic Transducers). This suppression system includes a transfer function and a simple P (proportion) controller, which can reduce the ring-down time without degrading any performances of PMUTs. The transfer function serves as a virtual PMUT device, feeding its output into the P controller; then, the P controller generates a suppression signal to the actual PMUT device. The ring-down time of a 115-kHz PMUT array is demonstrated to be reduced by up to 93% through the suppression system. In addition, the P controller has been experimentally optimized, reducing the blind area of the PMUT array by about 40%. Moreover, a low ring-down PMUTs system design guideline is established, which is practical and straightforward for industrial scenarios. Finally, the system can be easily integrated into ASIC (Application Specific Integrated Circuit).

THE DEEP TIME OF BITCOIN: EXCAVATING THE "WORK" IN PROOF-OF-WORK CRYPTOCURRENCY SYSTEMS

Estimates place Bitcoin’s current energy consumption at 141.83 terawatt-hours/year, an amount comparable to Ukraine. While Bitcoin’s energy problem has become increasingly visible in both academic and popular discourse (see Lally et al. 2019), the computational mechanisms through which the Bitcoin network generates coins, proof-of-work, has gone under-examined. This paper interrogates the “work” in proof-of-work systems. What is this work? How can we access its material history? I trace this history through a media archaeology of computational heat, in an attempt to better situate the intimate relationship between information and energy in proof-of-work systems. I argue the “work” in these systems is principally heat-work, and trace its ideological constructions back to nineteenth-century thermodynamic science, and the reframing of doing work as something exhaustible, directional, and irreversible (Prigogine & Stengers 2017; Daggett 2019). I then follow thermodynamic discourse through Cybernetics debates in the 1940s, illustrating how, early in the formation of Information Theory, the heat-work undergirding the functioning of a “bit” was obscured and compartmentalized, allowing information to be productively abstracted apart from its energetic infrastructures (Hayles 1999; Kline 2015). I conclude with a discussion of the heat-work within the Application Specific Integrated Circuit (ASIC), Bitcoin’s principal mining tool, arguing that proof-of-work mining is not a radical exception to the computing status quo, but rather a lens through which to think more broadly about computing’s complex relationship to energy, and ultimately, how this relationship can be different.

HOBFLOPS for CNNs: Hardware Optimized Bitslice-Parallel Floating-Point Operations for Convolutional Neural Networks

Low-precision floating-point (FP) can be highly effective for convolutional neural network (CNN) inference. Custom low-precision FP can be implemented in field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) accelerators, but existing microprocessors do not generally support fast, custom precision FP. We propose hardware optimized bitslice-parallel floating-point operators (HOBFLOPS), a generator of efficient custom precision emulated bitslice-parallel software(C/C++) FP arithmetic. We generate custom-precision FP routines, optimized using a hardware synthesis design flow, to create circuits. We provide standard cell libraries matching the bitwise operations on the target microprocessor architecture and a code generator to translate the hardware circuits to bitslice software equivalents. We exploit bitslice parallelism to create a novel, very wide (32—512 element) vectorized CNN convolution for inference. On Arm and Intel processors, the multiply-accumulate (MAC) performance in CNN convolution of HOBFLOPS, Flexfloat, and Berkeley’s SoftFP are compared. HOBFLOPS outperforms Flexfloat by up to 10× on Intel AVX512. HOBFLOPS offers arbitrary-precision FP with custom range and precision, e . g ., HOBFLOPS9, which outperforms Flexfloat 9-bit on Arm Neon by 7×. HOBFLOPS allows researchers to prototype different levels of custom FP precision in the arithmetic of software CNN ac celerators. Furthermore, HOBFLOPS fast custom-precision FP CNNs may be valuable in cases where memory bandwidth is limited.

Fast IQ Amplitude Approximation Method for ASIC Digital System

In some modules of digital systems, such as Fast Fourier Transform (FFT), Discrete Fourier transform (DFT), IQ (in-phase and quadrature components) modulation/ demodulation, the outputs use the complex data formed , and the calculation of its magnitude value √ are required. In software digital signal processing platform, the multiplication and square root operations are executed by using its math library; however, in Application specific integrated circuit (ASIC) digital system design, the implementation of those operators via Coordinate Rotation Digital Computer (CORDIC) algorithm requires the numerous resources and delays. So, in this paper, we present a fast approximation method for above problem which takes a small delay but acceptable accuracy for AISC digital system design. Keywords—ASIC, Digital system design, FFT, DFT, Fast amplitude approximation, Max-Min approximation.

AES-LBBB: AES Mode for Lightweight and BBB-Secure Authenticated Encryption

In this paper, a new lightweight authenticated encryption scheme AESLBBB is proposed, which was designed to provide backward compatibility with advanced encryption standard (AES) as well as high security and low memory. The primary design goal, backward compatibility, is motivated by the fact that AES accelerators are now very common for devices in the field; we are interested in designing an efficient and highly secure mode of operation that exploits the best of those AES accelerators. The backward compatibility receives little attention in the NIST lightweight cryptography standardization process, in which only 3 out of 32 round-2 candidates are based on AES. Our mode, LBBB, is inspired by the design of ALE in the sense that the internal state size is a minimum 2n bits when using a block cipher of length n bits for the key and data. Unfortunately, there is no security proof of ALE, and forgery attacks have been found on ALE. In LBBB, we introduce an additional feed from block cipher’s output to the key state via a certain permutation λ, which enables us to prove beyond-birthday-bound (BBB) security. We then specify its AES instance, AES-LBBB, and evaluate its performance for (i) software implementation on a microcontroller with an AES coprocessor and (ii) hardware implementation for an application-specific integrated circuit (ASIC) to show that AES-LBBB performs better than the current state-of-the-art Remus-N2 with AES-128.