hardware scheduling
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Author(s):  
Xiang Gong ◽  
Zhongliang Chen ◽  
Amir Kavyan Ziabari ◽  
Rafael Ubal ◽  
David Kaeli


IEEE Micro ◽  
2015 ◽  
Vol 35 (4) ◽  
pp. 37-47
Author(s):  
Nikola Markovic ◽  
Daniel Nemirovsky ◽  
Osman Unsal ◽  
Mateo Valero ◽  
Adrian Cristal


2015 ◽  
Vol 71 (6) ◽  
pp. 2309-2338 ◽  
Author(s):  
Behram Khan ◽  
Daniel Goodman ◽  
Salman Khan ◽  
Will Toms ◽  
Paolo Faraboschi ◽  
...  




Author(s):  
Ogier Maitre ◽  
Nicolas Lachiche ◽  
Pierre Collet


Author(s):  
Andre C. Nacul ◽  
Francesco Regazzoni ◽  
Marcello Lajolo
Keyword(s):  


1998 ◽  
Vol 08 (02) ◽  
pp. 301-314
Author(s):  
SILVIA M. MUELLER ◽  
WOLFGANG J. PAUL

Hardware scheduling mechanisms are commonly used in current processors in order to make better use of instruction level parallelism. So far, such a mechanism is considered to be correct, if it avoids the standard structural and data hazards. However, based on two classical scheduling mechanisms, it will be shown that this condition is neither sufficient nor necessary for the correctness of such a mechanism, and that deadlocks are a serious matter in out-of-order execution as well. In addition, the paper provides sufficient conditions for the correctness of scheduling mechanisms.



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