Low complexity Turbo synchronization without initial carrier synchronization

Wireless data transmission results in frequency and phase offsets of the signal in the receiver. In addition the received symbols are corrupted by noise. Therefore synchronization and channel coding are vital parts of each receiver in digital communication systems. By combining the phase and frequency synchronization with an advanced iterative channel decoder (inner loop) like turbo codes in an iterative way (outer loop), the communications performance can be increased. This principal is referred to as turbo synchronization. For turbo synchronization an initial estimate of phase and frequency offset is required. In this paper we study the case, where the initial carrier synchronization is omitted and an approach with trial frequencies is chosen. We present novel techniques to minimize the number of trial frequencies to be processed. The communications performance and effort of our method is demonstrated. Furthermore the implementation complexity of the whole system is shown on a Xilinx FPGA.

Analysis of iteration control for turbo decoders in turbo synchronization applications

Wireless data transmission results in frequency and phase offsets of the signal in the receiver. In addition, the received symbols are corrupted by noise. Therefore, synchronization and channel coding are vital parts of each receiver in digital communication systems. By combining the phase and frequency synchronization with an advanced iterative channel decoder (inner loop) e.g. turbo codes in an iterative way (outer loop), the communications performance can be further increased. This principle is referred to as turbo synchronization. The energy consumption and the peak throughput of the system depend on the number of iterations for both loops. An advanced iteration control can decrease the mean number of needed iterations by detecting correctly decoded blocks. This leads to a dramatic energy saving or to an increase of throughput. In this paper we present a new stopping criterion for decodable blocks for turbo decoding in interrelation with turbo synchronization. Furthermore the implementation complexity of the turbo decoder is shown on a Xilinx FPGA.