Splay Tree Hybridized Multicriteria ant Colony and Bregman Divergencive Firefly Optimized Vlsi Floorplanning

Floorplanning is a basic designing step in VLSI circuit to estimate chip area before the optimized placement of digital blocks and their connections. The process of Floorplanning involves identifying the locations, shape, and size of components in a chip. The floorplanning is a hard problem since the consumption of energy and heat generation was high for the placement of modules. In order to improve the optimized floor planning, a novel Splay tree Hybridized Multicriteria Ant Colony and Bregman Divergencive Firefly Optimized Floor Planning (STHMAC-BDFOFP) technique is proposed. Main objective of STHMAC-BDFOFP technique is to efficient floor planning with minimum time. Initially, a number of modules are given with their connections obtained from benchmark dataset. In STHMAC-BDFOFP, a Splay tree-based non-slicing floor planning model constructing trees via modeling geometric relationship among modules. A splay tree is build after performing different operations namely splaying, join, split, insertion, and deletion on modules for floor planning. The constructed floorplan design is optimized by Hybridized Multicriteria Ant Colony and Bregman Divergencive Firefly algorithm. At first, the ant colony optimization is applied for finding the local optimum solution from the population of modules in the Splay tree with Multicriteria functions namely energy consumption, heat generation, space occupied, and wire length. Depends on fitness measure, the local optimum solution is determined. Then the global solution is attained by applying the Bregman Divergencive Firefly ranked algorithm. In this way, optimum modules in the splay tree are identified and obtain efficient floorplanning in VLSI design. Discussed results indicate that STHMAC-BDFOFP technique improves the performance of energy and heat aware floor planning as compared to conventional works.

MFMW: Modified Floor planning with Minimum Wire length

Floorplanning is one of the most critical phases inVLSI circuit design. The module alignment has a substantial concentration on the minimization of chip area and total wirelength in slicing floorplan. At foremost, the disadvantages of dead space are investigated and an instinctive and profligate method is proposed to find the equitable part of component. Then, a tormenting for standardized expression is improved to produce new solution, and the proposed simulated annealing algorithm which improves design efficiency is opted for the best floorplan solution. The proposed MFMW method attains less area on the commonly used AMI33 and AMI 49 benchmark circuits.