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2007 IEEE International High Level Design Validation and Test Workshop
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TOTAL DOCUMENTS
41
(FIVE YEARS 0)
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7
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Published By IEEE
9781424414802
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Table of contents
2007 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2007.4392774
◽
2007
◽
Download Full-text
Functional coverage measurements and results in post-Silicon validation of Core™2 duo family
2007 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2007.4392804
◽
2007
◽
Cited By ~ 19
Author(s):
Tommy Bojan
◽
Manuel Aguilar Arreola
◽
Eran Shlomo
◽
Tal Shachar
Keyword(s):
Functional Coverage
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Automatic error diagnosis and correction for RTL designs
2007 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2007.4392789
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2007
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Cited By ~ 10
Author(s):
Kai-hui Chang
◽
Ilya Wagner
◽
Valeria Bertacco
◽
Igor L. Markov
Keyword(s):
Error Diagnosis
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Automatic Error
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Circuit design and verication with Esterel v7 and Esterel Studio
2007 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2007.4392800
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2007
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Cited By ~ 4
Author(s):
Gerard Berry
Keyword(s):
Circuit Design
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Towards RTL test generation from SystemC TLM specifications
2007 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2007.4392793
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2007
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Cited By ~ 5
Author(s):
Mingsong Chen
◽
Prabhat Mishra
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Dhrubajyoti Kalita
Keyword(s):
Test Generation
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AME: an abstract middleware environment for validating networked embedded systems applications
2007 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2007.4392812
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2007
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Cited By ~ 1
Author(s):
F. Fummi
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G. Perbellini
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D. Quaglia
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S. Vinco
Keyword(s):
Embedded Systems
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Networked Embedded Systems
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Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip
2007 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2007.4392782
◽
2007
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Cited By ~ 12
Author(s):
Eric Cheung
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Harry Hsieh
◽
Felice Balarin
Keyword(s):
System On Chip
◽
Multiprocessor System
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Buffer Sizing
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On Chip
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Challenges in post-silicon verification of IBM’s Cell/B.E. and other game processors
2007 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2007.4392785
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2007
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Author(s):
Shakti Kapoor
Keyword(s):
Silicon Verification
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Session 2: Multiprocessors 11
2007 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2007.4392779
◽
2007
◽
Download Full-text
An approach for computing the initial state for retimed synchronous sequential circuits
2007 IEEE International High Level Design Validation and Test Workshop
◽
10.1109/hldvt.2007.4392798
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2007
◽
Author(s):
Noureddine Chabini
◽
Wayne Wolf
Keyword(s):
Sequential Circuits
◽
Initial State
◽
Synchronous Sequential Circuits
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