2007 IEEE International High Level Design Validation and Test Workshop
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9781424414802

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2007 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2007.4392774 ◽

2007 ◽

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Functional coverage measurements and results in post-Silicon validation of Core™2 duo family

2007 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2007.4392804 ◽

2007 ◽

Cited By ~ 19

Author(s):

Tommy Bojan ◽

Manuel Aguilar Arreola ◽

Eran Shlomo ◽

Tal Shachar

Keyword(s):

Functional Coverage

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Automatic error diagnosis and correction for RTL designs

2007 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2007.4392789 ◽

2007 ◽

Cited By ~ 10

Author(s):

Kai-hui Chang ◽

Ilya Wagner ◽

Valeria Bertacco ◽

Igor L. Markov

Keyword(s):

Error Diagnosis ◽

Automatic Error

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Circuit design and verication with Esterel v7 and Esterel Studio

2007 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2007.4392800 ◽

2007 ◽

Cited By ~ 4

Author(s):

Gerard Berry

Keyword(s):

Circuit Design

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Towards RTL test generation from SystemC TLM specifications

2007 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2007.4392793 ◽

2007 ◽

Cited By ~ 5

Author(s):

Mingsong Chen ◽

Prabhat Mishra ◽

Dhrubajyoti Kalita

Keyword(s):

Test Generation

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Post-silicon verification methodology on Sun’s UItraSPARC T2

2007 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2007.4392784 ◽

2007 ◽

Cited By ~ 2

Author(s):

Jai Kumar ◽

Catherine Ahlschlager ◽

Peter Isberg

Keyword(s):

Verification Methodology ◽

Silicon Verification

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Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip

2007 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2007.4392782 ◽

2007 ◽

Cited By ~ 12

Author(s):

Eric Cheung ◽

Harry Hsieh ◽

Felice Balarin

Keyword(s):

System On Chip ◽

Multiprocessor System ◽

Buffer Sizing ◽

On Chip

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Challenges in post-silicon verification of IBM’s Cell/B.E. and other game processors

2007 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2007.4392785 ◽

2007 ◽

Author(s):

Shakti Kapoor

Keyword(s):

Silicon Verification

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AME: an abstract middleware environment for validating networked embedded systems applications

2007 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2007.4392812 ◽

2007 ◽

Cited By ~ 1

Author(s):

F. Fummi ◽

G. Perbellini ◽

D. Quaglia ◽

S. Vinco

Keyword(s):

Embedded Systems ◽

Networked Embedded Systems

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Keynote

2007 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2007.4392775 ◽

2007 ◽

Download Full-text

2007 IEEE International High Level Design Validation and Test Workshop
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Table of contents

Functional coverage measurements and results in post-Silicon validation of Core™2 duo family

Automatic error diagnosis and correction for RTL designs

Circuit design and verication with Esterel v7 and Esterel Studio

Towards RTL test generation from SystemC TLM specifications

Post-silicon verification methodology on Sun’s UItraSPARC T2

Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip

Challenges in post-silicon verification of IBM’s Cell/B.E. and other game processors

AME: an abstract middleware environment for validating networked embedded systems applications

Keynote

Export Citation Format

2007 IEEE International High Level Design Validation and Test WorkshopLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Table of contents

Functional coverage measurements and results in post-Silicon validation of Core™2 duo family

Automatic error diagnosis and correction for RTL designs

Circuit design and verication with Esterel v7 and Esterel Studio

Towards RTL test generation from SystemC TLM specifications

Post-silicon verification methodology on Sun’s UItraSPARC T2

Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip

Challenges in post-silicon verification of IBM’s Cell/B.E. and other game processors

AME: an abstract middleware environment for validating networked embedded systems applications

Keynote

2007 IEEE International High Level Design Validation and Test Workshop
Latest Publications