Verification Methodology for Simulation Models of the Synchronous Generator on Transients Analysis

During transients that occur in an electric network, large currents can flow and large electromagnetic torques can be developed in electric generators. Accurate calculation of currents and magnetic fields during transients is an important element in the optimal design of generators and network parts, as well as mechanical parts of machines and other torque transmission parts. This paper describes the modeling of a sudden three-phase short-circuit on a synchronous generator using the finite element method (FEM) and the dynamic model. The model for simulations that use the FEM was built in the MagNet software package, and the dynamic model is embedded in the MATLAB/Simulink software package. The dynamic simulation model of a part of a network with two identical generators, represented by equivalent parameters, was developed. The results obtained after the simulation of a sudden three-phase fault in the generators by both methods are presented, including three-phase voltages, three-phase currents, machine speeds, excitation voltages, and mechanical power. In particular, the short-circuit current in the phase with the highest peak value was analyzed to determine the accuracy of the equivalent parameters used in the dynamic model. Finally, the results of these two calculation methods are compared, and recommendations are presented for the application of different modeling methods.

Verification of Wishbone Bus Interface for SoC using System Verilog and UVM

The Verification phase carries important role in design cycle of a system on chip. Verification gives with the actual enactment and functionality of a DUT and to verify the design meets the system requirements. This paper present wishbone bus interface for soc integration to interconnect architecture for portable IP cores and test bench is developed in system Verilog and verification is done by both system Verilog verification methodology and universal verification methodology which includes scoreboard, functional coverage and assertion. This paper based on two application to integrate IP cores that is single master with single slave interconnection and single master with multiple slave interconnections where master is test bench and slave will be a core.

Router1x3 Protocol Design Implementation and Verification with Virtual Cut through Mechanism for Network on Chip (NoC)

Hundreds of processors and memory cores are implemented on a single substrate called the System on Chip (SoC). The SoC with bus-based architecture has restrictions on the processing speed of the system and as the design becomes complex and the issue of scalability arises. Hence NoC is designed to enhance the scalability, data reliability, and processing speed with low power consumption by decoupling communication from computations [1]. Using NoC the IP cores of SoC are connected through on-chip routers and send data to each other through packet switching. The router is a processing chip that decides the right path for data transmission, hence the efficient design of the router is essential to enhance the performance and throughput of the system [2]. To reduces latency through the switch, the Virtual cut-through mechanism is a packet switching technique, in which the switch starts forwarding a packet as soon as the destination address is processed by header. Hence the present work focuses on a router input-output protocol design with the Virtual Cut-through mechanism for closed-loop communication. Router 1x3 has a single input port and three output ports. The architecture of Router 1x3 with sub-modules such as FIFO, FSM, Synchronizer, and Register is designed analyzed and verified using Verilog, System Verilog language, and Universal Verification Methodology(UVM). And it is also implemented on Xilinx 14.5 IDE with Spartan-6- XC6SLX45 FPGA.

Verification of AMBA AHB Protocol using UVM

The project aims to verify the AMBA AHB protocol by using universal verification methodology is presented in this paper. Advanced high-performance(AHB) is used for communication of on chip bus which support single clock edge operation wider data 32/64/128 bit can be supported. The new verification constructs can be easily reused for the objected-oriented feature of universal verification methodology (UVM). Verification IP is the one which provides a smart way to verify the AHB Components. The advanced verification testbench incorporates the illustrations regarding simulation result are analysed to evaluate the effectiveness of the proposed testbench and functional coverage is to check functionality of the design. The self-checking mechanism using assertions improves the quality of UVM check by shortening time to debug and reducing time to cover for the in-depth understanding of test case output.

Verification of Dual Port RAM using System Verilog and UVM

Verification process place a prominent role in the field of SoC and ASIC design. Several verification methodologies are there apart from those Universal Verification Methodology (UVM) is advanced and it is widely used by the industries due to its special features. UVM provides reusable and well-structured verification components by using System Verilog class library. In this work, Dual Port RAM is considered as Design Under Test (DUT). System Verilog and UVM verification environments are developed to verify the DUT. Assertion and cover group coverage are set up with a goal of achieving 100% from both the environments.

Verification of WAFC in-flight icing forecasts using satellite observations

<p>In-flight icing constitutes a major hazard to aviation, and so it is vital to be able to forecast the risk of icing accurately. The Met Office is one of two World Area Forecast Centres (WAFC) to routinely produce and validate icing forecasts. The existing verification methodology of Bowyer and Gill (2018) evaluates each WAFC forecast against satellite-derived icing potential. However, the methodology currently evaluates the full Global forecast data, whereas satellite-derived icing potential is only available during daytime. At night, the presence of cloud is reported, and so only correct rejections and false alarms are possible during nocturnal hours.</p><p>We first present an extension to the existing verification methodology by restricting the analysis to only include daytime data and demonstrate that this significantly reduces the degree of over-forecasting previously reported. In addition, we examine the performance of the new WAFC icing severity forecasts and compare against the routine product, during Winter 2020/2021.</p><p>There are two major challenges when comparing forecast icing severity and forecast icing potential. The first is that we are comparing the potential for an icing event to occur with its predicted intensity. The second challenge is that the new severity forecasts are on a 0.25º grid, compared with 1.25º for icing potential.</p><p>We present results both under the assumption that moderate icing potential is the same as moderate icing severity, and as an independent comparison with a new satellite-derived icing severity product. We also test the sensitivity to the choice of verification grid by re-gridding to both 0.25º and 1.25º.</p><p>The results show that WAFC icing severity is over-predicted when compared with satellite-derived severity, especially over the tropics. However, icing events are likely to be too infrequent in the observations, and so the magnitude of the over-prediction is over-estimated. All forecasts show regional skill at predicting icing severity and the results are not sensitive to the choice of verification grid. However, the performance of the higher resolution icing severity forecast is likely to influenced by the double penalty problem.</p>

A Python based Design Verification Methodology

While the UVM-constrained random and coverage-driven verification methodology revolutionized IP and unit-level testing, it falls short of SoC-level verification needs. A solution must extend from UVM and enable vertical (IP to SoC) and horizontal (verification engine portability) reuse to completely handle SoC-level verification. To expedite test-case generation and use rapid verification engines, it must also provide a method to collect, distribute, and automatically amplify use cases. Opting a Python-based Design Verification approach opens the door to various such merits. Cocotb is a very useful, growing methodology which can be used for the same. This paper elaborates on the application of cocotb, an open-source framework hosted on Github which is based on CO-routine and CO-simulation of Testbench environment for verifying VHDL/Verilog RTL using Python. It employs equivalent design-reuse and functional verification concepts like UVM, however is implemented in Python, which is much simpler to understand and that leads to faster development and reduces the turnaround time.