2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS)
Latest Publications

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(FIVE YEARS 80)

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(FIVE YEARS 0)

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9781665419130

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

EILE: Efficient Incremental Learning on the Edge

2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) ◽

10.1109/aicas51828.2021.9458554 ◽

2021 ◽

Author(s):

Xi Chen ◽

Chang Gao ◽

Tobi Delbruck ◽

Shih-Chii Liu

Keyword(s):

Incremental Learning

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FPGA-accelerated Agent-Based Simulation for COVID-19

2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) ◽

10.1109/aicas51828.2021.9458570 ◽

2021 ◽

Author(s):

Lei Fu ◽

Ce Guo ◽

Wayne Luk

Keyword(s):

Agent Based Simulation ◽

Agent Based

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A Quality-Oriented Reconfigurable Convolution Engine Using Cross-Shaped Sparse Kernels for Highly-Parallel CNN Acceleration

2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) ◽

10.1109/aicas51828.2021.9458472 ◽

2021 ◽

Author(s):

Chi-Wen Weng ◽

Chao-Tsung Huang

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Evaluation of Machine Learning-based Detection against Side-Channel Attacks on Autonomous Vehicle

2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) ◽

10.1109/aicas51828.2021.9458488 ◽

2021 ◽

Author(s):

Han Wang ◽

Soheil Salehi ◽

Hossein Sayadi ◽

Avesta Sasan ◽

Tinoosh Mohsenin ◽

...

Keyword(s):

Machine Learning ◽

Autonomous Vehicle ◽

Side Channel ◽

Side Channel Attacks

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LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation

2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) ◽

10.1109/aicas51828.2021.9458493 ◽

2021 ◽

Author(s):

Arne Symons ◽

Linyan Mei ◽

Marian Verhelst

Keyword(s):

Memory Allocation ◽

Loop Order

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Design Tools for Resistive Crossbar based Machine Learning Accelerators

2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) ◽

10.1109/aicas51828.2021.9458433 ◽

2021 ◽

Author(s):

Indranil Chakraborty ◽

Sourjya Roy ◽

Shrihari Sridharan ◽

Mustafa Ali ◽

Aayush Ankit ◽

...

Keyword(s):

Machine Learning ◽

Design Tools

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Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks

2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) ◽

10.1109/aicas51828.2021.9458553 ◽

2021 ◽

Author(s):

Vikram Jain ◽

Linyan Mei ◽

Marian Verhelst

Keyword(s):

Neural Networks ◽

Trade Off ◽

Energy Latency

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Hardware Approximation of Exponential Decay for Spiking Neural Networks

2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) ◽

10.1109/aicas51828.2021.9458560 ◽

2021 ◽

Author(s):

Sherif Eissa ◽

Sander Stuijk ◽

Henk Corporaal

Keyword(s):

Neural Networks ◽

Exponential Decay ◽

Spiking Neural Networks

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Trends in Analog and Digital Intensive Compute-in-SRAM Designs

2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) ◽

10.1109/aicas51828.2021.9458576 ◽

2021 ◽

Author(s):

Rishabh Sehgal ◽

Jaydeep P. Kulkarni

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An Ultra-Low Latency Multicast Router for Large-Scale Multi-Chip Neuromorphic Processing

2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) ◽

10.1109/aicas51828.2021.9458445 ◽

2021 ◽

Author(s):

Chen Ding ◽

Yuxiang Huan ◽

Hao Jia ◽

Yulong Yan ◽

Fanxi Yang ◽

...

Keyword(s):

Large Scale ◽

Low Latency

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2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

EILE: Efficient Incremental Learning on the Edge

FPGA-accelerated Agent-Based Simulation for COVID-19

A Quality-Oriented Reconfigurable Convolution Engine Using Cross-Shaped Sparse Kernels for Highly-Parallel CNN Acceleration

Evaluation of Machine Learning-based Detection against Side-Channel Attacks on Autonomous Vehicle

LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation

Design Tools for Resistive Crossbar based Machine Learning Accelerators

Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks

Hardware Approximation of Exponential Decay for Spiking Neural Networks

Trends in Analog and Digital Intensive Compute-in-SRAM Designs

An Ultra-Low Latency Multicast Router for Large-Scale Multi-Chip Neuromorphic Processing

2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS)
Latest Publications