Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
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Published By Springer New York

9781441995414, 9781441995421

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Modeling of Atomic Concentration at the Wire-to-TSV Interface

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits ◽

10.1007/978-1-4419-9542-1_9 ◽

2012 ◽

pp. 231-250

Author(s):

Sung Kyu Lim

Keyword(s):

Atomic Concentration ◽

The Wire

Impact of TSV Scaling on 3D IC Design Quality

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits ◽

10.1007/978-1-4419-9542-1_19 ◽

2012 ◽

pp. 515-535

Author(s):

Sung Kyu Lim

Keyword(s):

Ic Design ◽

Design Quality ◽

3D Ic

Chip/Package Co-analysis of Mechanical Stress for 3D IC

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits ◽

10.1007/978-1-4419-9542-1_15 ◽

2012 ◽

pp. 415-441

Author(s):

Sung Kyu Lim

Keyword(s):

Mechanical Stress ◽

3D Ic

TSV Current Crowding and Power Integrity

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits ◽

10.1007/978-1-4419-9542-1_8 ◽

2012 ◽

pp. 205-229

Author(s):

Sung Kyu Lim

Keyword(s):

Current Crowding ◽

Power Integrity

Steiner Routing for 3D IC

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits ◽

10.1007/978-1-4419-9542-1_2 ◽

2012 ◽

pp. 41-73

Author(s):

Sung Kyu Lim

Keyword(s):

3D Ic

3D-MAPS: 3D Massively Parallel Processor with Stacked Memory

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits ◽

10.1007/978-1-4419-9542-1_20 ◽

2012 ◽

pp. 537-560 ◽

Cited By ~ 12

Author(s):

Sung Kyu Lim

Keyword(s):

Massively Parallel ◽

Parallel Processor ◽

Massively Parallel Processor ◽

Stacked Memory

Low Power Clock Routing for 3D IC

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits ◽

10.1007/978-1-4419-9542-1_4 ◽

2012 ◽

pp. 99-128

Author(s):

Sung Kyu Lim

Keyword(s):

Low Power ◽

3D Ic ◽

Clock Routing

3D Chip/Package Co-analysis of Stress-Induced Timing Variations

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits ◽

10.1007/978-1-4419-9542-1_16 ◽

2012 ◽

pp. 443-465

Author(s):

Sung Kyu Lim

Impact of Mechanical Stress on Timing Variation for 3D IC

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits ◽

10.1007/978-1-4419-9542-1_14 ◽

2012 ◽

pp. 379-414

Author(s):

Sung Kyu Lim

Keyword(s):

Mechanical Stress ◽

3D Ic

Power Delivery Network Design for 3D IC

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits ◽

10.1007/978-1-4419-9542-1_5 ◽

2012 ◽

pp. 129-151

Author(s):

Sung Kyu Lim

Keyword(s):

Network Design ◽

Power Delivery ◽

3D Ic ◽

Power Delivery Network ◽

Delivery Network

Design for High Performance, Low Power, and Reliable 3D Integrated CircuitsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer New York

Modeling of Atomic Concentration at the Wire-to-TSV Interface

Impact of TSV Scaling on 3D IC Design Quality

Chip/Package Co-analysis of Mechanical Stress for 3D IC

TSV Current Crowding and Power Integrity

Steiner Routing for 3D IC

3D-MAPS: 3D Massively Parallel Processor with Stacked Memory

Low Power Clock Routing for 3D IC

3D Chip/Package Co-analysis of Stress-Induced Timing Variations

Impact of Mechanical Stress on Timing Variation for 3D IC

Power Delivery Network Design for 3D IC

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
Latest Publications