Design Automation and Test Solutions for Monolithic 3D ICs

Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes the limitations of the conventional through-silicon-via (TSV) and provides significant performance uplift and power reduction. However, the ultra-dense 3D interconnects impose significant challenges during physical design on how to best utilize them. Besides, the unique low-temperature fabrication process of M3D requires dedicated design-for-test mechanisms to verify the reliability of the chip. In this article, we provide an in-depth analysis on these design and test challenges in M3D. We also provide a comprehensive survey of the state-of-the-art solutions presented in the literature. This article encompasses all key steps on M3D physical design, including partitioning, placement, clock routing, and thermal analysis and optimization. In addition, we provide an in-depth analysis of various fault mechanisms, including M3D manufacturing defects, delay faults, and MIV (monolithic inter-tier via) faults. Our design-for-test solutions include test pattern generation for pre/post-bond testing, built-in-self-test, and test access architectures targeting M3D.

IMPROVED DELAY AND PROCESS VARIATION TOLERANT CLOCK TREE NETWORK IN ULTRA-LARGE CIRCUITS USING HYBRID RF/METAL CLOCK ROUTING

Clock distribution has been a major limitation on delay, power and routing resources in ultra-large nanoscale circuits. Some emerging technologies are proposed to use RF instruments for on-chip clock routing in large chips but they suffer from large power and area overheads. In this paper, a hybrid radio frequency (RF) and metal clock networking architecture corresponding with an efficient RF and metal clock routing is presented which combines the benefits of RF/wireless interconnect and metal/wired connections to reach a reasonable trade-off between RF and metal interconnect technologies. Our experiments show that clock network delay and clock tree congestion is improved by 61% and 40% on average. Moreover, sensitivity of attempted benchmarks to process variation of interconnects is reduced considerably. These improvements are gained at a cost of less than 2% of area overhead and less than 10% power consumption overhead for large circuits. It is shown that overheads are very small for large circuits such that this technology will be completely feasible and reasonable for too large and complex circuits.