IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94
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0818663073

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On soft switch programming for reconfigurable array systems

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94 ◽

10.1109/dftvs.1994.630031 ◽

2002 ◽

Author(s):

T. Liu ◽

F. Lombardi

Keyword(s):

Soft Switch ◽

Reconfigurable Array

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A fault-tolerant associative approach to on-line memory repair

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94 ◽

10.1109/dftvs.1994.630027 ◽

2002 ◽

Cited By ~ 1

Author(s):

Jien-Chung Lo

Keyword(s):

Fault Tolerant ◽

On Line ◽

Memory Repair

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Implementation of a gracefully degradable binary tree in programmable multi-chip modules

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94 ◽

10.1109/dftvs.1994.630011 ◽

2002 ◽

Author(s):

S. Goldberg ◽

S.J. Upadhyaya

Keyword(s):

Binary Tree

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On the analysis of routing, cells and adjacency faults in CMOS digital circuits

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94 ◽

10.1109/dftvs.1994.630038 ◽

2002 ◽

Cited By ~ 1

Author(s):

A.P. Casimiro ◽

M.B. Santos ◽

F. Goncalves ◽

J.P. Teixeira

Keyword(s):

Digital Circuits

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Fault-tolerant modular convolvers

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94 ◽

10.1109/dftvs.1994.630012 ◽

2002 ◽

Author(s):

L. Dadda ◽

V. Piuri

Keyword(s):

Fault Tolerant

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Augmenting scan path SRLs with an XOR network to enhance delay fault testing

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94 ◽

10.1109/dftvs.1994.630014 ◽

2002 ◽

Cited By ~ 3

Author(s):

Zaifu Zhang ◽

R.D. McLeod ◽

W. Pedrycz

Keyword(s):

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Scan Path

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Efficient critical area algorithms and their application to yield improvement and test strategies

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94 ◽

10.1109/dftvs.1994.630018 ◽

2002 ◽

Cited By ~ 14

Author(s):

G.A. Allan ◽

A.J. Walton

Keyword(s):

Critical Area ◽

Yield Improvement ◽

Test Strategies

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Alternative approaches to fault detection in FSMs

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94 ◽

10.1109/dftvs.1994.630040 ◽

2002 ◽

Cited By ~ 6

Author(s):

R. Leveugle ◽

R. Rochet ◽

G. Saucier

Keyword(s):

Fault Detection ◽

Alternative Approaches

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Yield enhancement with particle defects reduction

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94 ◽

10.1109/dftvs.1994.630036 ◽

2002 ◽

Cited By ~ 3

Author(s):

K. Mori ◽

N. Nguyen ◽

D. Keeton ◽

R. Burns

Keyword(s):

Yield Enhancement

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CMOS self checking circuits with faulty sequential functional blocks

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94 ◽

10.1109/dftvs.1994.630023 ◽

2002 ◽

Cited By ~ 3

Author(s):

C. Metra ◽

M. Favalli ◽

B. Ricco

Keyword(s):

Functional Blocks

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IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

On soft switch programming for reconfigurable array systems

A fault-tolerant associative approach to on-line memory repair

Implementation of a gracefully degradable binary tree in programmable multi-chip modules

On the analysis of routing, cells and adjacency faults in CMOS digital circuits

Fault-tolerant modular convolvers

Augmenting scan path SRLs with an XOR network to enhance delay fault testing

Efficient critical area algorithms and their application to yield improvement and test strategies

Alternative approaches to fault detection in FSMs

Yield enhancement with particle defects reduction

CMOS self checking circuits with faulty sequential functional blocks

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems DFTVS-94
Latest Publications