Proceedings of 9th International Symposium on Systems Synthesis
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Published By IEEE Comput. Soc. Press

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Synthesis of low-power selectively-clocked systems from high-level specification

Proceedings of 9th International Symposium on Systems Synthesis ◽

10.1109/isss.1996.565878 ◽

2002 ◽

Cited By ~ 6

Author(s):

L. Benini ◽

P. Vuillod ◽

G. De Micheli ◽

C. Coelho

Keyword(s):

Low Power ◽

High Level

Testability insertion in behavioral descriptions

Proceedings of 9th International Symposium on Systems Synthesis ◽

10.1109/isss.1996.565896 ◽

2002 ◽

Cited By ~ 2

Author(s):

F.F. Hsu ◽

E.M. Rudnick ◽

J.H. Patel

DSP processor/compiler co-design: a quantitative approach

Proceedings of 9th International Symposium on Systems Synthesis ◽

10.1109/isss.1996.565890 ◽

2002 ◽

Cited By ~ 4

Author(s):

V. Zivojnovic ◽

S. Pees ◽

C. Schlager ◽

M. Willems ◽

R. Schoenen ◽

...

Keyword(s):

Quantitative Approach

Hardware/software partitioning with iterative improvement heuristics

Proceedings of 9th International Symposium on Systems Synthesis ◽

10.1109/isss.1996.565881 ◽

2002 ◽

Cited By ~ 11

Author(s):

P. Eles ◽

Zebo Peng ◽

K. Kuchcinski ◽

A. Doboli

Keyword(s):

Iterative Improvement ◽

Software Partitioning

Bus-based communication synthesis on system-level

Proceedings of 9th International Symposium on Systems Synthesis ◽

10.1109/isss.1996.565880 ◽

2002 ◽

Cited By ~ 21

Author(s):

M. Gasteier ◽

M. Glesner

Keyword(s):

System Level ◽

Communication Synthesis

Breakpoints and breakpoint detection in source level emulation

Proceedings of 9th International Symposium on Systems Synthesis ◽

10.1109/isss.1996.565873 ◽

2002 ◽

Cited By ~ 4

Author(s):

G. Koch ◽

U. Kebschull ◽

W. Rosenstiel

Keyword(s):

Breakpoint Detection ◽

Source Level

Memory organization for improved data cache performance in embedded processors

Proceedings of 9th International Symposium on Systems Synthesis ◽

10.1109/isss.1996.565886 ◽

2002 ◽

Cited By ~ 30

Author(s):

P. Panda ◽

N. Dutt ◽

A. Nicolau

Keyword(s):

Embedded Processors ◽

Data Cache ◽

Memory Organization ◽

Cache Performance

Modeling multicomputer task allocation as a vector packing problem

Proceedings of 9th International Symposium on Systems Synthesis ◽

10.1109/isss.1996.565892 ◽

2002 ◽

Cited By ~ 7

Author(s):

J.E. Beck ◽

D.P. Siewiorek

Keyword(s):

Task Allocation ◽

Packing Problem

Grammar-based hardware synthesis of data communication protocols

Proceedings of 9th International Symposium on Systems Synthesis ◽

10.1109/isss.1996.565871 ◽

2002 ◽

Cited By ~ 19

Author(s):

J. Oberg ◽

A. Kumar ◽

A. Hemani

Keyword(s):

Communication Protocols ◽

Data Communication ◽

Hardware Synthesis

System-level synthesis of application specific systems using A* search and generalized force-directed heuristics

Proceedings of 9th International Symposium on Systems Synthesis ◽

10.1109/isss.1996.565869 ◽

2002 ◽

Author(s):

Chunho Lee ◽

K. Potkonjak ◽

W. Wolf

Keyword(s):

System Level ◽

Generalized Force ◽

Application Specific

Proceedings of 9th International Symposium on Systems SynthesisLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

Synthesis of low-power selectively-clocked systems from high-level specification

Testability insertion in behavioral descriptions

DSP processor/compiler co-design: a quantitative approach

Hardware/software partitioning with iterative improvement heuristics

Bus-based communication synthesis on system-level

Breakpoints and breakpoint detection in source level emulation

Memory organization for improved data cache performance in embedded processors

Modeling multicomputer task allocation as a vector packing problem

Grammar-based hardware synthesis of data communication protocols

System-level synthesis of application specific systems using A* search and generalized force-directed heuristics

Proceedings of 9th International Symposium on Systems Synthesis
Latest Publications