Proceedings of IEEE VLSI Test Symposium
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71

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Published By IEEE Comput. Soc. Press

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Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

On-line delay testing of digital circuits

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292318 ◽

2002 ◽

Cited By ~ 44

Author(s):

P. Franco ◽

E.J. McCluskey

Keyword(s):

Digital Circuits ◽

Delay Testing ◽

On Line

New advances in path delay fault testing of combinational circuits

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292301 ◽

2002 ◽

Cited By ~ 3

Author(s):

X. Xie ◽

A. Albicki

Keyword(s):

Path Delay ◽

Combinational Circuits ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

Three-pattern tests for delay faults

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292274 ◽

2002 ◽

Cited By ~ 27

Author(s):

P. Franco ◽

E.J. McCluskey

Keyword(s):

Delay Faults

Structural constraints for circular self-test paths

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292329 ◽

2002 ◽

Cited By ~ 11

Author(s):

J. Carletta ◽

C. Papachristou

Keyword(s):

Structural Constraints ◽

Self Test

Gate-to-channel shorts in BiCMOS logic gates

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292276 ◽

2002 ◽

Cited By ~ 2

Author(s):

C.-J. Chen ◽

S. Mourad

Keyword(s):

Logic Gates

On compacting test sets by addition and removal of test vectors

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292312 ◽

2002 ◽

Cited By ~ 28

Author(s):

S. Kajihara ◽

I. Pomeranz ◽

K. Kinoshita ◽

S.M. Reddy

Keyword(s):

Test Sets ◽

Test Vectors

Analyzing the design-for-test techniques in a multiple substrate MCM

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292288 ◽

2002 ◽

Cited By ~ 9

Author(s):

J.A. Jorgenson ◽

R.J. Wagner

Keyword(s):

Design For Test ◽

Multiple Substrate

CMOS bridging fault modeling

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292283 ◽

2002 ◽

Cited By ~ 34

Author(s):

M. Renovell ◽

P. Huc ◽

Y. Bertrand

Keyword(s):

Fault Modeling ◽

Bridging Fault

Impact of behavioral modifications for testability

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292278 ◽

2002 ◽

Cited By ~ 10

Author(s):

T. Thomas ◽

P. Vishakantantaiah ◽

J.A. Abraham

Aliasing error for a mask ROM built-in self-test

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292328 ◽

2002 ◽

Author(s):

K. Iwasaki ◽

A. Furuta ◽

S. Nakamura

Keyword(s):

Aliasing Error ◽

Self Test ◽

Built In Self Test