2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
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9781509036233

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Reliable PUF design using failure patterns from time-controlled power gating

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2016.7684085 ◽

2016 ◽

Cited By ~ 3

Author(s):

Xiaolin Xu ◽

Daniel E. Holcomb

Keyword(s):

Power Gating ◽

Failure Patterns

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Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2016.7684070 ◽

2016 ◽

Cited By ~ 3

Author(s):

Zaid Al-bayati ◽

Brett H. Meyer ◽

Haibo Zeng

Keyword(s):

Fault Tolerant ◽

Mixed Criticality

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Guiding Genetic Algorithms using importance measures for reliable design of embedded systems

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2016.7684069 ◽

2016 ◽

Cited By ~ 2

Author(s):

Hananeh Aliee ◽

Stefan Vitzethum ◽

Michael Glass ◽

Jurgen Teich ◽

Emanuele Borgonovo

Keyword(s):

Genetic Algorithms ◽

Embedded Systems ◽

Reliable Design

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A Highly Robust Double Node Upset Tolerant latch

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2016.7684062 ◽

2016 ◽

Cited By ~ 10

Author(s):

Adam Watkins ◽

Spyros Tragouodas

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A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2016.7684082 ◽

2016 ◽

Cited By ~ 4

Author(s):

Amir Charif ◽

Nacer-Eddine Zergainoh ◽

Michael Nicolaidis

Keyword(s):

High Performance ◽

Fault Tolerant ◽

Adaptive Routing ◽

New Approach ◽

Fully Adaptive

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Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2016.7684076 ◽

2016 ◽

Cited By ~ 10

Author(s):

Xabier Iturbe ◽

Balaji Venu ◽

Emre Ozer

Keyword(s):

Real Time ◽

Vulnerability Assessment ◽

Soft Error ◽

The Real

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Prognosis of NBTI aging using a machine learning scheme

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2016.7684060 ◽

2016 ◽

Cited By ~ 3

Author(s):

Naghmeh Karimi ◽

Ke Huang

Keyword(s):

Machine Learning ◽

Learning Scheme

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A novel method for SEE validation of complex SoCs using Low-Energy Proton beams

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2016.7684084 ◽

2016 ◽

Cited By ~ 2

Author(s):

Gianluca Furano ◽

Stefano Di Mascio ◽

Tomasz Szewczyk ◽

Alessandra Menicucci ◽

Luigi Campajola ◽

...

Keyword(s):

Low Energy ◽

Proton Beams ◽

Energy Proton ◽

Novel Method

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Low cost resilient regular expression matching on FPGAs

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2016.7684073 ◽

2016 ◽

Cited By ~ 3

Author(s):

Marcos T. Leipnitz ◽

Eduardo Nunes de Souza ◽

Gabriel L. Nazar

Keyword(s):

Regular Expression ◽

Low Cost ◽

Regular Expression Matching

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An adaptive routing algorithm to improve lifetime reliability in NoCs architecture

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2016.7684083 ◽

2016 ◽

Cited By ~ 1

Author(s):

Juman Alshraiedeh ◽

Avinash Kodi

Keyword(s):

Routing Algorithm ◽

Adaptive Routing ◽

Lifetime Reliability

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2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Reliable PUF design using failure patterns from time-controlled power gating

Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures

Guiding Genetic Algorithms using importance measures for reliable design of embedded systems

A Highly Robust Double Node Upset Tolerant latch

A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs

Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU

Prognosis of NBTI aging using a machine learning scheme

A novel method for SEE validation of complex SoCs using Low-Energy Proton beams

Low cost resilient regular expression matching on FPGAs

An adaptive routing algorithm to improve lifetime reliability in NoCs architecture

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Latest Publications