Euromicro Symposium on Digital System Design, 2003. Proceedings.
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68

(FIVE YEARS 0)

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9

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0769520030

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Sensor platform design for automotive applications

Euromicro Symposium on Digital System Design, 2003. Proceedings. ◽

10.1109/dsd.2003.1231966 ◽

2003 ◽

Author(s):

M. De Marinis ◽

L. Fanucci ◽

A. Giambastiani ◽

A. Reneiri ◽

A. Rocchi ◽

...

Keyword(s):

Automotive Applications ◽

Platform Design ◽

Sensor Platform

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Concurrent operation scheduling and unit allocation with an evolutionary technique

Euromicro Symposium on Digital System Design, 2003. Proceedings. ◽

10.1109/dsd.2003.1231977 ◽

2003 ◽

Author(s):

G. Papa ◽

J. Silc

Keyword(s):

Evolutionary Technique ◽

Operation Scheduling

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A development and simulation environment for a floating point operations FPGA based accelerator

Euromicro Symposium on Digital System Design, 2003. Proceedings. ◽

10.1109/dsd.2003.1231922 ◽

2003 ◽

Author(s):

M. Bera ◽

G. Danese ◽

I. De Lotto ◽

F. Leporati ◽

A. Spelgatti

Keyword(s):

Floating Point ◽

Simulation Environment

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Testable design verification using Petri nets

Euromicro Symposium on Digital System Design, 2003. Proceedings. ◽

10.1109/dsd.2003.1231960 ◽

2003 ◽

Author(s):

R. Ruzicka

Keyword(s):

Design Verification ◽

Testable Design

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A scheduling and partitioning scheme for low power circuit operating at multiple voltages

Euromicro Symposium on Digital System Design, 2003. Proceedings. ◽

10.1109/dsd.2003.1231915 ◽

2003 ◽

Author(s):

Ling Wang ◽

H. Selvaraj

Keyword(s):

Low Power ◽

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A power reduction scheme for data buses by dynamic detection of active bits

Euromicro Symposium on Digital System Design, 2003. Proceedings. ◽

10.1109/dsd.2003.1231974 ◽

2003 ◽

Author(s):

M. Muroyama ◽

A. Hyodo ◽

T. Okuma ◽

H. Yasuura

Keyword(s):

Power Reduction ◽

Reduction Scheme ◽

Dynamic Detection ◽

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Reconfigurable randomized K-way graph partitioning

Euromicro Symposium on Digital System Design, 2003. Proceedings. ◽

10.1109/dsd.2003.1231947 ◽

2003 ◽

Author(s):

F. Kocan

Keyword(s):

Graph Partitioning

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Estimating the utilization of embedded FPGA co-processor

Euromicro Symposium on Digital System Design, 2003. Proceedings. ◽

10.1109/dsd.2003.1231929 ◽

2003 ◽

Author(s):

Yang Qu ◽

J.-P. Soininen

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An efficient implementation of fair load balancing over multi-CPU SOC architectures

Euromicro Symposium on Digital System Design, 2003. Proceedings. ◽

10.1109/dsd.2003.1231925 ◽

2003 ◽

Author(s):

G. Kornaros ◽

T. Orphanoudakis ◽

N. Zervos

Keyword(s):

Load Balancing ◽

Efficient Implementation

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FC-Min: a fast multi-output Boolean minimizer

Euromicro Symposium on Digital System Design, 2003. Proceedings. ◽

10.1109/dsd.2003.1231982 ◽

2003 ◽

Author(s):

P. Fiser ◽

J. Hlavicka ◽

H. Kubatova

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