testable design
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Delay Testable Design Using Modified Boundary Scan

2021 ◽  
Vol 24 (7) ◽  
pp. 663-667
Author(s):  
Hiroyuki Yotsuyanagi ◽  
Masaki Hashizume
Keyword(s):  
Boundary Scan ◽  
Testable Design

Testable design of control digital automatic machines

2020 ◽  
Author(s):  
Maryna Miroshnyk ◽  
Olexander Shkil ◽  
Dariia Rakhlis ◽  
Inna Filippenko ◽  
Elvira Kulak ◽  
...  
Keyword(s):  
Testable Design

Testable Design of Reversible Circuits Using Parity Preserving Gates

2018 ◽  
Vol 35 (4) ◽  
pp. 56-64 ◽  
Author(s):  
Hari Mohan Gaur ◽  
Ashutosh Kumar Singh ◽  
Umesh Ghanekar
Keyword(s):  
Reversible Circuits ◽  
Testable Design

scholarly journals A Testable Design Method for Memories by Boundary Scan Technique

2016 ◽  
Vol 7 ◽  
pp. 04006
Author(s):  
Guo-Hui Qiao ◽  
Zhong-Liang Deng ◽  
Ke Han ◽  
Dong-Yang Yao ◽  
Zhi-Heng Yue
Keyword(s):  
Design Method ◽  
Boundary Scan ◽  
Testable Design

A testable design for electrical interconnect tests of 3D ICs

2015 ◽  
Author(s):  
Akihiro Odoriba ◽  
Shoichi Umezu ◽  
Masaki Hashizume ◽  
Hiroyuki Yotsuyanagi ◽  
Fara Ashikin Binti Ali ◽  
...  
Keyword(s):  
3D Ics ◽  
Testable Design

Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs

2013 ◽  
Author(s):  
Masaki Hashizume ◽  
Tomoaki Konishi ◽  
Hiroyuki Yotsuyanag ◽  
Shyue-Kung Lu
Keyword(s):  
3D Ics ◽  
Open Defects ◽  
Testable Design

Hardware Testable Design of Genetic Algorithm for VLSI Circuits

2013 ◽  
Vol 367 ◽  
pp. 245-249
Author(s):  
N. Rajeswaran ◽  
T. Madhu ◽  
M. Suryakalavathi
Keyword(s):  
Artificial Intelligence ◽  
Digital Circuits ◽  
Input Sequence ◽  
Digital Circuit ◽  
Vlsi Circuits ◽  
Computational Time ◽  
Artificial Intelligence Technique ◽  
Real Time Applications ◽  
Testable Design ◽  
Intelligence Technique

Accurate and fast testing of digital circuits is very much essential in real time applications. Hardware analysis of digital circuits, which is otherwise very tedious and time consuming, is attempted using the artificial intelligence technique: Genetic Algorithms (GA). GA is used to find an input sequence to a digital circuit for testing, as it reduces the hardware utilization, complexity and computational time of the circuits. All the GA processes are simulated and implemented by using Xilinx 10.1 and SPARTAN 3E.

scholarly journals Testable Design of RF-ICs using BIST Technique

2012 ◽  
Vol 13 (4) ◽  
pp. 491-500
Author(s):  
Yong Kim ◽  
Jae-Min Lee
Keyword(s):  
Testable Design ◽  
Rf Ics
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