Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)
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Garp: a MIPS processor with a reconfigurable coprocessor

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) ◽

10.1109/fpga.1997.624600 ◽

2002 ◽

Author(s):

J.R. Hauser ◽

J. Wawrzynek

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Implementation of single precision floating point square root on FPGAs

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) ◽

10.1109/fpga.1997.624623 ◽

2002 ◽

Author(s):

Yamin Li ◽

Wanming Chu

Keyword(s):

Floating Point ◽

Square Root ◽

Single Precision

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An FPGA-based coprocessor for ATM firewalls

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) ◽

10.1109/fpga.1997.624602 ◽

2002 ◽

Author(s):

J.T. McHenry ◽

P.W. Dowd ◽

F.A. Pellegrino ◽

T.M. Carrozzi ◽

W.B. Cocks

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The Chimaera reconfigurable functional unit

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) ◽

10.1109/fpga.1997.624608 ◽

2002 ◽

Author(s):

S. Hauck ◽

T.W. Fry ◽

M.M. Hosler ◽

J.P. Kao

Keyword(s):

Functional Unit

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On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) ◽

10.1109/fpga.1997.624629 ◽

2002 ◽

Author(s):

J. Cong ◽

J. Peck

Keyword(s):

Logic Synthesis ◽

Synthesis Algorithm

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The swappable logic unit: a paradigm for virtual hardware

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) ◽

10.1109/fpga.1997.624607 ◽

2002 ◽

Author(s):

G. Brebner

Keyword(s):

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Acceleration of an FPGA router

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) ◽

10.1109/fpga.1997.624617 ◽

2002 ◽

Author(s):

P.K. Chan ◽

M.D.F. Schlag

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High level compilation for fine grained FPGAs

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) ◽

10.1109/fpga.1997.624616 ◽

2002 ◽

Author(s):

M. Gokhale ◽

D. Gomersall

Keyword(s):

Fine Grained ◽

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A dynamic reconfiguration run-time system

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) ◽

10.1109/fpga.1997.624606 ◽

2002 ◽

Author(s):

J. Burns ◽

A. Donlin ◽

J. Hogg ◽

S. Singh ◽

M. De Wit

Keyword(s):

Dynamic Reconfiguration ◽

Time System ◽

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Laser defect correction applications to FPGA based custom computers

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) ◽

10.1109/fpga.1997.624626 ◽

2002 ◽

Author(s):

G.H. Chapman ◽

B. Dufort

Keyword(s):

Defect Correction

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