A Stable 4-Bit ALU Design for Printed Devices

Printed devices fabricated using roll-to-roll (R2R) printing technology have been used in low-cost Internet of Things (IoTs), smart packaging and bio-chips. As the area of applications of printed devices broadens, arithmetic units in digital design need to be implemented. In this paper, we propose a stable 4-bit arithmetic logic unit (ALU) design using a minimum number of transistors that can overcome the limitations of printed devices. We propose the use of a 2:1 transmission gate (TG) multiplexer (MUX) structure and hybrid 16T full-adder to construct the ALU. New design methods are applied to reduce the number of inverter stages added to overcome the voltage degradation. Using this approach reduces the total number of transistors used in the design from 276 to 153, compared to the conventional design, with significant improvements in delay and power performance.

Design and Performance Analysis of Low Power High Speed Adder and Multiplier Using MTCMOS in 90nm, 70nm, 25nm and 18nm Regime

Nowadays, VLSI technology mainly focused on High-Speed Propagation and Low Power Consumption. Addition is an important arithmetic operation which plays a major role in digital application. Adder is act as an important role in the applications of signal processing, in memory access address generation and Arithmetic Logic Unit. When the number of transistors increases in system designs, makes to increase power and complexity of the circuit. One of the dominant factors is power reduction in low power VLSI technology and to overcome the power dissipation in the existing adder circuit, MTCMOS technique is used in the proposed adder. The design is simulated in 90nm, 70nm, 25nm and 18nm technology and then comparison is made between existing and proposed system in the context of energy, area and delay. In this comparison, the efficiency metrics power and delay are found to be reduced 20% from the existing adder and the proposed adder is used for the design of low power multiplier.

Efficient Designs of Quantum Adder/Subtractor Using Universal Reversible Gate on IBM Q

Reversible arithmetic and logic unit (ALU) is a necessary part of quantum computing. In this work, we present improved designs of reversible half and full addition and subtraction circuits. The proposed designs are based on a universal one type gate (G gate library). The G gate library can generate all possible permutations of the symmetric group. The presented designs are multi-function circuits that are capable of performing additional logical operations. We achieve a reduction in the quantum cost, gate count, number of constant inputs, and delay with zero garbage, compared to relevant results obtained by others. The experimental results using IBM Quantum Experience (IBM Q) illustrate the success probability of the proposed designs.

An Advanced 1-bit Arithmetic Logic Unit (ALU) with Hybrid Memristor-CMOS Architecture

<div>Memristor is dubbed as the fourth fundamental electrical component which works primarily as a non-volatile memory element. Memristors can also be used to construct logic gates, and Memristor Ratioed Logic (MRL) is one of these structures. The higher area efficiency and CMOS architecture compatibility of MRL gates have lead researchers to pay attention to its use in digital logic architecture. In this work, binary MRL is integrated with Complementary Metal-Oxide Semiconductor(CMOS) logic elements to develop building blocks of an Arithmetic Logic Unit (ALU). The proposed 1-bit ALU is simulated using LTSpice, which allows the versatility of changing the parameters as per the model used. This work designs and analyses an optimized cascadable 1-bit ALU with with voltage level based binary logic state via simulation. The proposed circuit shows improvement in transistor count and delay over benchmark circuits.</div>

An Advanced 1-bit Arithmetic Logic Unit (ALU) with Hybrid Memristor-CMOS Architecture

<div>Memristor is dubbed as the fourth fundamental electrical component which works primarily as a non-volatile memory element. Memristors can also be used to construct logic gates, and Memristor Ratioed Logic (MRL) is one of these structures. The higher area efficiency and CMOS architecture compatibility of MRL gates have lead researchers to pay attention to its use in digital logic architecture. In this work, binary MRL is integrated with Complementary Metal-Oxide Semiconductor(CMOS) logic elements to develop building blocks of an Arithmetic Logic Unit (ALU). The proposed 1-bit ALU is simulated using LTSpice, which allows the versatility of changing the parameters as per the model used. This work designs and analyses an optimized cascadable 1-bit ALU with with voltage level based binary logic state via simulation. The proposed circuit shows improvement in transistor count and delay over benchmark circuits.</div>