Implementation of single precision floating point square root on FPGAs

2002 ◽  
Author(s):  
Yamin Li ◽  
Wanming Chu
Keyword(s):  
Floating Point ◽  
Square Root ◽  
Single Precision

scholarly journals A Modification of the Fast Inverse Square Root Algorithm

Computation ◽  
2019 ◽  
Vol 7 (3) ◽  
pp. 41 ◽  
Author(s):  
Cezary J. Walczyk ◽  
Leonid V. Moroz ◽  
Jan L. Cieśliński
Keyword(s):  
Analytical Approach ◽  
Floating Point ◽  
Square Root ◽  
Approximate Evaluation ◽  
Single Precision ◽  
Seed Solution ◽  
Numerical Tests ◽  
Newton Raphson ◽  
Relative Errors ◽  
Magic Constant

We present a new algorithm for the approximate evaluation of the inverse square root for single-precision floating-point numbers. This is a modification of the famous fast inverse square root code. We use the same “magic constant” to compute the seed solution, but then, we apply Newton–Raphson corrections with modified coefficients. As compared to the original fast inverse square root code, the new algorithm is two-times more accurate in the case of one Newton–Raphson correction and almost seven-times more accurate in the case of two corrections. We discuss relative errors within our analytical approach and perform numerical tests of our algorithm for all numbers of the type float.

scholarly journals A Modification of the Fast Inverse Square Root Algorithm

2019 ◽  
Author(s):  
Cezary J. Walczyk ◽  
Leonid V. Moroz ◽  
Jan L. Cieśliński
Keyword(s):  
Computational Cost ◽  
Floating Point ◽  
Square Root ◽  
Single Precision ◽  
Fast Calculation ◽  
Newton Raphson ◽  
Floating Point Numbers ◽  
Improved Algorithm

We present an improved algorithm for fast calculation of the inverse square root for single-precision floating-point numbers. The algorithm is much more accurate than the famous fast inverse square root algorithm and has a similar computational cost. The presented modification concern Newton-Raphson corrections and can be applied when the distribution of these corrections is not symmetric (for instance, in our case they are always negative).

scholarly journals Approximate Reciprocal Square Root with Single - and Half-Precision Floats

2018 ◽  
Author(s):  
Matheus M. Susin ◽  
Lucas Wanner
Keyword(s):  
Power Consumption ◽  
Floating Point ◽  
Square Root ◽  
Single Precision ◽  
Approximation Techniques ◽  
Point Number ◽  
Floating Point Number ◽  
Floating Point Numbers

In this work, we compared the precision, speed, and power consumption of the reciprocal square root of a single-precision floating point number, using different approximation techniques. We also devised an equivalent approximation for half-precision floating point numbers, and evaluated its performance across the whole range of positive non-zero 16-bit floating point values.

scholarly journals A Low-Cost High Radix Floating-Point Square-Root Circuit

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1988
Author(s):  
Yuheng Yang ◽  
Qing Yuan ◽  
Jian Liu
Keyword(s):  
Power Consumption ◽  
Low Cost ◽  
Floating Point ◽  
Square Root ◽  
Single Precision ◽  
Dynamic Power ◽  
Low Area ◽  
High Radix

In this paper, we propose an efficient architecture of floating-point square-root circuit with low area cost, which is in accordance with the IEEE-754 standard. We extend the principle of the standard SRT algorithm so that the latency and area cost of the proposed circuit are linear with the radix. In addition, no extra computation cycles are required. With 65 nm technology, the area cost of the single-precision floating-point square-root circuit based on proposed architecture is only 6450.84 μm2, and the dynamic power consumption is only 0.764 mW at 300 MHz. The implementation results show that the proposed square-root circuit can reduce the area cost by 60%~90% compared with other designs in the literature.

scholarly journals Research on IEEE 754 Standard Single Precision Floating Point Multipliers Designed using Urdhva Triyagbhyam Sutra of Vedic Mathematics

2019 ◽  
Vol 8 (2S11) ◽  
pp. 2990-2993
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Single Precision ◽  
Vedic Mathematics ◽  
Quadruple Precision

Duplication of the coasting element numbers is the big activity in automated signal handling. So the exhibition of drifting problem multipliers count on a primary undertaking in any computerized plan. Coasting factor numbers are spoken to utilizing IEEE 754 modern day in single precision(32-bits), Double precision(sixty four-bits) and Quadruple precision(128-bits) organizations. Augmentation of those coasting component numbers can be completed via using Vedic generation. Vedic arithmetic encompass sixteen wonderful calculations or Sutras. Urdhva Triyagbhyam Sutra is most usually applied for growth of twofold numbers. This paper indicates the compare of tough work finished via exceptional specialists in the direction of the plan of IEEE 754 ultra-modern-day unmarried accuracy skimming thing multiplier the usage of Vedic technological statistics.

scholarly journals NULL Convention Floating Point Multiplier

2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Anitha Juliette Albert ◽  
Seshasayanan Ramachandran
Keyword(s):  
High Precision ◽  
Dynamic Range ◽  
Digital Signal ◽  
High Dynamic Range ◽  
Floating Point ◽  
Single Precision ◽  
Critical Part ◽  
Point Multiplication ◽  
Null Convention Logic ◽  
High Dynamic

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.

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