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2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)
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22
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Published By IEEE
9781509013869
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Message from the advisory committee chair
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)
◽
10.1109/coolchips.2016.7503664
◽
2016
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Author(s):
Tadao Nakamura
Keyword(s):
Advisory Committee
◽
Committee Chair
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Powering-off DRAM with aggressive page-out to storage-class memory in low power virtual memory system
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)
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10.1109/coolchips.2016.7503675
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2016
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Cited By ~ 2
Author(s):
Yusuke Shirota
◽
Shiyo Yoshimura
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Satoshi Shirai
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Tatsunori Kanai
Keyword(s):
Low Power
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Virtual Memory
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Memory System
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Storage Class Memory
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[Front matter]
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)
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10.1109/coolchips.2016.7503662
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2016
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Download Full-text
Message from the program committee chairs
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)
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10.1109/coolchips.2016.7503665
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2016
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Author(s):
Makoto Ikeda
◽
Fumio Arakawa
Keyword(s):
Program Committee
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How SIMD width affects energy efficiency: A case study on sorting
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)
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10.1109/coolchips.2016.7503679
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2016
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Cited By ~ 6
Author(s):
Hiroshi Inoue
Keyword(s):
Energy Efficiency
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A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)
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10.1109/coolchips.2016.7503681
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2016
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Cited By ~ 11
Author(s):
Megumi Ito
◽
Moriyoshi Ohara
Keyword(s):
Systolic Array
◽
Coherent Interface
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Power Efficient
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Special session speaker's biography
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)
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10.1109/coolchips.2016.7503668
◽
2016
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Keyword(s):
Special Session
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A cache partitioning mechanism to protect shared data for CMPs
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)
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10.1109/coolchips.2016.7503674
◽
2016
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Cited By ~ 1
Author(s):
Masayuki Sato
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Shin Nishimura
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Ryusuke Egawa
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Hiroyuki Takizawa
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Hiroaki Kobayashi
Keyword(s):
Cache Partitioning
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Shared Data
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A 1.1 mW 32-thread artificial intelligence processor with 3-level transposition table and on-chip PVT compensation for autonomous mobile robots
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)
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10.1109/coolchips.2016.7503671
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2016
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Author(s):
Youchang Kim
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Dongjoo Shin
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Jinsu Lee
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Hoi-Jun Yoo
Keyword(s):
Artificial Intelligence
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Mobile Robots
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Autonomous Mobile Robots
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On Chip
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Keynote & invited speaker's biography
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)
◽
10.1109/coolchips.2016.7503669
◽
2016
◽
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