2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)
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(FIVE YEARS 0)

Published By IEEE

9781509013869

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Powering-off DRAM with aggressive page-out to storage-class memory in low power virtual memory system

2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX) ◽

10.1109/coolchips.2016.7503675 ◽

2016 ◽

Cited By ~ 2

Author(s):

Yusuke Shirota ◽

Shiyo Yoshimura ◽

Satoshi Shirai ◽

Tatsunori Kanai

Keyword(s):

Low Power ◽

Virtual Memory ◽

Memory System ◽

Storage Class Memory

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Message from the advisory committee chair

2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX) ◽

10.1109/coolchips.2016.7503664 ◽

2016 ◽

Author(s):

Tadao Nakamura

Keyword(s):

Advisory Committee ◽

Committee Chair

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[Front matter]

2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX) ◽

10.1109/coolchips.2016.7503662 ◽

2016 ◽

Download Full-text

Special session speaker's biography

2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX) ◽

10.1109/coolchips.2016.7503668 ◽

2016 ◽

Keyword(s):

Special Session

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How SIMD width affects energy efficiency: A case study on sorting

2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX) ◽

10.1109/coolchips.2016.7503679 ◽

2016 ◽

Cited By ~ 6

Author(s):

Hiroshi Inoue

Keyword(s):

Energy Efficiency

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A cache partitioning mechanism to protect shared data for CMPs

2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX) ◽

10.1109/coolchips.2016.7503674 ◽

2016 ◽

Cited By ~ 1

Author(s):

Masayuki Sato ◽

Shin Nishimura ◽

Ryusuke Egawa ◽

Hiroyuki Takizawa ◽

Hiroaki Kobayashi

Keyword(s):

Cache Partitioning ◽

Shared Data

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A 1.1 mW 32-thread artificial intelligence processor with 3-level transposition table and on-chip PVT compensation for autonomous mobile robots

2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX) ◽

10.1109/coolchips.2016.7503671 ◽

2016 ◽

Author(s):

Youchang Kim ◽

Dongjoo Shin ◽

Jinsu Lee ◽

Hoi-Jun Yoo

Keyword(s):

Artificial Intelligence ◽

Mobile Robots ◽

Autonomous Mobile Robots ◽

On Chip

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A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm

2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX) ◽

10.1109/coolchips.2016.7503681 ◽

2016 ◽

Cited By ~ 11

Author(s):

Megumi Ito ◽

Moriyoshi Ohara

Keyword(s):

Systolic Array ◽

Coherent Interface ◽

Power Efficient

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Message from the program committee chairs

2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX) ◽

10.1109/coolchips.2016.7503665 ◽

2016 ◽

Author(s):

Makoto Ikeda ◽

Fumio Arakawa

Keyword(s):

Program Committee

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Keynote & invited speaker's biography

2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX) ◽

10.1109/coolchips.2016.7503669 ◽

2016 ◽

Download Full-text

2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Powering-off DRAM with aggressive page-out to storage-class memory in low power virtual memory system

Message from the advisory committee chair

[Front matter]

Special session speaker's biography

How SIMD width affects energy efficiency: A case study on sorting

A cache partitioning mechanism to protect shared data for CMPs

A 1.1 mW 32-thread artificial intelligence processor with 3-level transposition table and on-chip PVT compensation for autonomous mobile robots

A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm

Message from the program committee chairs

Keynote & invited speaker's biography

2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)
Latest Publications