Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09
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MinDeg

Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09 ◽

10.1145/1629435.1629481 ◽

2009 ◽

Cited By ~ 3

Author(s):

Lars Bauer ◽

Muhammad Shafique ◽

Jörg Henkel

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Improving application launch times with hybrid disks

Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09 ◽

10.1145/1629435.1629486 ◽

2009 ◽

Cited By ~ 5

Author(s):

Yongsoo Joo ◽

Youngjin Cho ◽

Kyungsoo Lee ◽

Naehyuck Chang

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Statistical physics approaches for network-on-chip traffic characterization

Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09 ◽

10.1145/1629435.1629498 ◽

2009 ◽

Cited By ~ 36

Author(s):

Paul Bogdan ◽

Radu Marculescu

Keyword(s):

Statistical Physics ◽

Network On Chip ◽

Traffic Characterization ◽

On Chip

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An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking

Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09 ◽

10.1145/1629435.1629445 ◽

2009 ◽

Cited By ~ 15

Author(s):

Weichen Liu ◽

Zonghua Gu ◽

Jiang Xu ◽

Yu Wang ◽

Mingxuan Yuan

Keyword(s):

Model Checking ◽

Efficient Technique ◽

Dataflow Graphs ◽

Synchronous Dataflow ◽

Synchronous Dataflow Graphs

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Scalable and retargetable simulation techniquesfor multiprocessor systems

Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09 ◽

10.1145/1629435.1629448 ◽

2009 ◽

Cited By ~ 8

Author(s):

Heekyung Kim ◽

Dukyoung Yun ◽

Soonhoi Ha

Keyword(s):

Multiprocessor Systems

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TotalProf

Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09 ◽

10.1145/1629435.1629477 ◽

2009 ◽

Cited By ~ 14

Author(s):

Lei Gao ◽

Jia Huang ◽

Jianjiang Ceng ◽

Rainer Leupers ◽

Gerd Ascheid ◽

...

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A scalable parallel H.264 decoder on the cell broadband engine architecture

Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09 ◽

10.1145/1629435.1629484 ◽

2009 ◽

Cited By ~ 8

Author(s):

Michael A. Baker ◽

Pravin Dalale ◽

Karam S. Chatha ◽

Sarma B.K. Vrudhula

Keyword(s):

Cell Broadband Engine

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A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures

Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09 ◽

10.1145/1629435.1629451 ◽

2009 ◽

Cited By ~ 9

Author(s):

Leonel Tedesco ◽

Fabien Clermidy ◽

Fernando Moraes

Keyword(s):

Adaptive Routing ◽

Routing Mechanism

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Automated technique for design of NoC with minimal communication latency

Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09 ◽

10.1145/1629435.1629499 ◽

2009 ◽

Cited By ~ 6

Author(s):

Glenn Leary ◽

Karam S. Chatha

Keyword(s):

Communication Latency ◽

Automated Technique

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On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices

Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09 ◽

10.1145/1629435.1629457 ◽

2009 ◽

Cited By ~ 9

Author(s):

David Szczesny ◽

Sebastian Hessel ◽

Felix Bruns ◽

Attila Bilgic

Keyword(s):

Mobile Devices ◽

Hardware Acceleration ◽

Protocol Stack ◽

Next Generation

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Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

MinDeg

Improving application launch times with hybrid disks

Statistical physics approaches for network-on-chip traffic characterization

An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking

Scalable and retargetable simulation techniquesfor multiprocessor systems

TotalProf

A scalable parallel H.264 decoder on the cell broadband engine architecture

A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures

Automated technique for design of NoC with minimal communication latency

On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices

Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '09
Latest Publications