ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference
Latest Publications

TOTAL DOCUMENTS

125

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(FIVE YEARS 0)

Published By IEEE

9781509029723

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference ◽

10.1109/esscirc.2016.7598268 ◽

2016 ◽

Cited By ~ 1

Author(s):

Ashish Kumar ◽

Chandrajit Debnath ◽

Pratap Narayan Singh ◽

Vivek Bhatia ◽

Shivani Chaudhary ◽

...

Keyword(s):

Single Channel ◽

Calibration Free

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An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference ◽

10.1109/esscirc.2016.7598335 ◽

2016 ◽

Cited By ~ 3

Author(s):

Zhao Chuan Lee ◽

M. Sultan M. Siddiqui ◽

Zhi Hui Kong ◽

Tony Tae-Hyoung Kim

Keyword(s):

Two Phase ◽

Cell Stability ◽

28 Nm

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An LC-DCO based synthesizable injection-locked PLL with an FoM of −250.3dB

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference ◽

10.1109/esscirc.2016.7598276 ◽

2016 ◽

Cited By ~ 2

Author(s):

Dongsheng Yang ◽

Wei Deng ◽

Bangan Liu ◽

Teerachot Siriburanon ◽

Kenichi Okada ◽

...

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Bang-bang digital PLLs

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference ◽

10.1109/esscirc.2016.7598309 ◽

2016 ◽

Cited By ~ 3

Author(s):

Salvatore Levantino

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Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference ◽

10.1109/esscirc.2016.7598280 ◽

2016 ◽

Cited By ~ 2

Author(s):

Cheng-Ru Ho ◽

Mike Shuo-Wei Chen

Keyword(s):

Phase Locked Loop ◽

Digital Phase

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A 3.5–6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference ◽

10.1109/esscirc.2016.7598279 ◽

2016 ◽

Cited By ~ 1

Author(s):

Ying Wu ◽

Mina Shahmohammadi ◽

Yue Chen ◽

Ping Lu ◽

Robert Bogdan Staszewski

Keyword(s):

Phase Noise ◽

Wide Bandwidth

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Reflection amplifier based on graphene

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference ◽

10.1109/esscirc.2016.7598243 ◽

2016 ◽

Author(s):

Pankaj Sharma ◽

Laurent Syavoch Bernard ◽

Antonios Bazigos ◽

Arnaud Magrez ◽

Laszlo Forro ◽

...

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A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/°C fully integrated current-mode RC oscillator for real-time clock applications with PVT stability

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference ◽

10.1109/esscirc.2016.7598264 ◽

2016 ◽

Cited By ~ 2

Author(s):

H. Asano ◽

T. Hirose ◽

K. Tsubaki ◽

T. Miyoshi ◽

T. Ozaki ◽

...

Keyword(s):

Real Time ◽

Current Mode ◽

Fully Integrated ◽

Real Time Clock

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ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference ◽

10.1109/esscirc.2016.7598229 ◽

2016 ◽

Download Full-text

Gate driver with 10 / 15ns in-transition variable drive current and 60% reduced current dip

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference ◽

10.1109/esscirc.2016.7598308 ◽

2016 ◽

Cited By ~ 1

Author(s):

Alexis Schindler ◽

Benno Koeppl ◽

Ansgar Pottbaecker ◽

Markus Zannoth ◽

Bernhard Wicht

Keyword(s):

Drive Current ◽

Gate Driver

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ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB

An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI

An LC-DCO based synthesizable injection-locked PLL with an FoM of −250.3dB

Bang-bang digital PLLs

Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS

A 3.5–6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

Reflection amplifier based on graphene

A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/°C fully integrated current-mode RC oscillator for real-time clock applications with PVT stability

Table of contents

Gate driver with 10 / 15ns in-transition variable drive current and 60% reduced current dip

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ESSCIRC Conference 2016: 42nd European Solid-State Circuits ConferenceLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB

An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI

An LC-DCO based synthesizable injection-locked PLL with an FoM of −250.3dB

Bang-bang digital PLLs

Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS

A 3.5–6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

Reflection amplifier based on graphene

A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/°C fully integrated current-mode RC oscillator for real-time clock applications with PVT stability

Table of contents

Gate driver with 10 / 15ns in-transition variable drive current and 60% reduced current dip

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference
Latest Publications