Proceedings of the conference on Design, automation and test in Europe - DATE '99
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147

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Published By ACM Press

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Minimizing sensitivity to delay variations in high-performance synchronous circuits

Proceedings of the conference on Design, automation and test in Europe - DATE '99 ◽

10.1145/307418.307581 ◽

1999 ◽

Author(s):

Xun Liu ◽

Marios C. Papaefthymiou ◽

Eby G. Friedman

Keyword(s):

High Performance ◽

Synchronous Circuits ◽

Delay Variations

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Design methodology for IP providers

Proceedings of the conference on Design, automation and test in Europe - DATE '99 ◽

10.1145/307418.307599 ◽

1999 ◽

Cited By ~ 5

Author(s):

Jürgen Haase

Keyword(s):

Design Methodology

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A retargetable, ultra-fast instruction set simulator

Proceedings of the conference on Design, automation and test in Europe - DATE '99 ◽

10.1145/307418.307509 ◽

1999 ◽

Cited By ~ 27

Author(s):

Jianwen Zhu ◽

Daniel D. Gajski

Keyword(s):

Instruction Set

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Efficient techniques for accurate extraction and modeling of substrate coupling in mixed-signal IC's

Proceedings of the conference on Design, automation and test in Europe - DATE '99 ◽

10.1145/307418.307531 ◽

1999 ◽

Cited By ~ 2

Author(s):

João Paulo Costa ◽

Mike Chou ◽

L. Miguel Silveira

Keyword(s):

Mixed Signal ◽

Substrate Coupling

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Reuse of IP and virtual components

Proceedings of the conference on Design, automation and test in Europe - DATE '99 ◽

10.1145/307418.307598 ◽

1999 ◽

Cited By ~ 4

Author(s):

Ralf Seepold

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Interval diagram techniques for symbolic model checking of Petri nets

Proceedings of the conference on Design, automation and test in Europe - DATE '99 ◽

10.1145/307418.307452 ◽

1999 ◽

Cited By ~ 6

Author(s):

Karsten Strehl ◽

Lothar Thiele

Keyword(s):

Model Checking ◽

Petri Nets ◽

Symbolic Model Checking ◽

Symbolic Model ◽

Diagram Techniques

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Channel-based behavioral test synthesis for improved module reachability

Proceedings of the conference on Design, automation and test in Europe - DATE '99 ◽

10.1145/307418.307506 ◽

1999 ◽

Author(s):

Yiorgos Makris ◽

Alex Orailoğlu

Keyword(s):

Behavioral Test ◽

Test Synthesis

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Peak power estimation using genetic spot optimization for large VLSI circuits

Proceedings of the conference on Design, automation and test in Europe - DATE '99 ◽

10.1145/307418.307484 ◽

1999 ◽

Cited By ~ 9

Author(s):

Michael S. Hsiao

Keyword(s):

Peak Power ◽

Power Estimation ◽

Vlsi Circuits

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FreezeFrame

Proceedings of the conference on Design, automation and test in Europe - DATE '99 ◽

10.1145/307418.307604 ◽

1999 ◽

Cited By ~ 1

Author(s):

Yanti Santoso ◽

Matthew Merten ◽

Elizabeth M. Rudnick ◽

Miron Abramovici

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Hardware synthesis from C/C++

Proceedings of the conference on Design, automation and test in Europe - DATE '99 ◽

10.1145/307418.307529 ◽

1999 ◽

Cited By ~ 6

Author(s):

Abhijit Ghosh ◽

Joachim Kunkel ◽

Stan Liao

Keyword(s):

Hardware Synthesis

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Proceedings of the conference on Design, automation and test in Europe - DATE '99Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Minimizing sensitivity to delay variations in high-performance synchronous circuits

Design methodology for IP providers

A retargetable, ultra-fast instruction set simulator

Efficient techniques for accurate extraction and modeling of substrate coupling in mixed-signal IC's

Reuse of IP and virtual components

Interval diagram techniques for symbolic model checking of Petri nets

Channel-based behavioral test synthesis for improved module reachability

Peak power estimation using genetic spot optimization for large VLSI circuits

FreezeFrame

Hardware synthesis from C/C++

Proceedings of the conference on Design, automation and test in Europe - DATE '99
Latest Publications