Innovative architecture for future generation high-performance processors and systems (iwia 2007)
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Innovative Architecture for Future Generation High-Performance Processors and Systems - Copyright

Innovative architecture for future generation high-performance processors and systems (iwia 2007) ◽

10.1109/iwia.2007.3 ◽

2007 ◽

Keyword(s):

High Performance ◽

Future Generation

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Innovative Architecture for Future Generation High-Performance Processors and Systems - Cover

Innovative architecture for future generation high-performance processors and systems (iwia 2007) ◽

10.1109/iwia.2007.21 ◽

2007 ◽

Keyword(s):

High Performance ◽

Future Generation

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Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems

Innovative architecture for future generation high-performance processors and systems (iwia 2007) ◽

10.1109/iwia.2007.7 ◽

2007 ◽

Author(s):

Jose L. Ayala ◽

Anya Apavatjrut ◽

David Atienza ◽

Marisa Lopez-Vallejo

Keyword(s):

Memory Architectures

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Responsive Link for Distributed Real-Time Processing

Innovative architecture for future generation high-performance processors and systems (iwia 2007) ◽

10.1109/iwia.2007.17 ◽

2007 ◽

Cited By ~ 12

Author(s):

Nobuyuki Yamasaki

Keyword(s):

Real Time ◽

Real Time Processing ◽

Time Processing

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Accelerating Brain Circuit Simulations of Object Recognition with CELL Processors

Innovative architecture for future generation high-performance processors and systems (iwia 2007) ◽

10.1109/iwia.2007.10 ◽

2007 ◽

Cited By ~ 2

Author(s):

Andrew Felch ◽

Jayram Moorkanikara Nageswaran ◽

Ashok Chandrashekar ◽

Jeff Furlong ◽

Nikil Dutt ◽

...

Keyword(s):

Object Recognition ◽

Brain Circuit ◽

Circuit Simulations

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Design Assists for Embedded Systems in the COINS Compiler Infrastructure

Innovative architecture for future generation high-performance processors and systems (iwia 2007) ◽

10.1109/iwia.2007.13 ◽

2007 ◽

Cited By ~ 2

Author(s):

Tan Watanabe ◽

Tetsuro Fujise ◽

Koichiro Mori ◽

Kyoko Iwasawa ◽

Ikuo Nakata

Keyword(s):

Embedded Systems ◽

Compiler Infrastructure

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Cache Memory Architecture for Leakage Energy Reduction

Innovative architecture for future generation high-performance processors and systems (iwia 2007) ◽

10.1109/iwia.2007.12 ◽

2007 ◽

Cited By ~ 3

Author(s):

Kiyofumi Tanaka

Keyword(s):

Energy Reduction ◽

Cache Memory ◽

Memory Architecture

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Innovative Architecture for Future Generation High-Performance Processors and Systems - TOC

Innovative architecture for future generation high-performance processors and systems (iwia 2007) ◽

10.1109/iwia.2007.6 ◽

2007 ◽

Keyword(s):

High Performance ◽

Future Generation

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Innovative Architecture for Future Generation High-Performance Processors and Systems - Title page

Innovative architecture for future generation high-performance processors and systems (iwia 2007) ◽

10.1109/iwia.2007.1 ◽

2007 ◽

Keyword(s):

High Performance ◽

Future Generation ◽

Title Page

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Implementation and Evaluation of Parallel FFT Using SIMD Instructions on Multi-core Processors

Innovative architecture for future generation high-performance processors and systems (iwia 2007) ◽

10.1109/iwia.2007.16 ◽

2007 ◽

Cited By ~ 7

Author(s):

Daisuke Takahashi

Keyword(s):

Parallel Fft

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Innovative architecture for future generation high-performance processors and systems (iwia 2007)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Innovative Architecture for Future Generation High-Performance Processors and Systems - Copyright

Innovative Architecture for Future Generation High-Performance Processors and Systems - Cover

Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems

Responsive Link for Distributed Real-Time Processing

Accelerating Brain Circuit Simulations of Object Recognition with CELL Processors

Design Assists for Embedded Systems in the COINS Compiler Infrastructure

Cache Memory Architecture for Leakage Energy Reduction

Innovative Architecture for Future Generation High-Performance Processors and Systems - TOC

Innovative Architecture for Future Generation High-Performance Processors and Systems - Title page

Implementation and Evaluation of Parallel FFT Using SIMD Instructions on Multi-core Processors

Innovative architecture for future generation high-performance processors and systems (iwia 2007)
Latest Publications