Performance Analysis of Acquisition Algorithms for Navic

Indian Regional Navigation Satellite System (IRNSS), is an indigenous navigation system designed and developed by ISRO (Indian Space Research Organization).It is named as NavIC, Navigation with Indian Constellation by Indian Prime Minister. NavIC is designed to have seven satellite constellation that provides reliable position, navigation and timing services over India. The focal modules of NavIC receiver are acquisition, tracking and navigation unit. Among them, acquisition is the data processing unit for detecting satellite signals and their corresponding code phase and carrier frequency. In this paper, various acquisition algorithms like Serial search and Parallel Code Phase search algorithms are analyzed and compared with Cooley-Tukey FFT algorithm and sub-sampled Fast Fourier transform (ssFFT).The results obtained in MATLAB shows that the acquisition computation time for ssFFT based NavIC receiver is faster than parallel FFT acquisition and the Cooley-Tukey FFT IRNSS acquisition algorithm is faster and provides better code phase and carrier frequency values compared to serial search acquisition algorithm.

Design of low- area, power fault tolerant parallel FFTs using trellis codes

Present day electronic circuits are generally affected by the delicate mistakes. To maintain the reliability of the complex systems few techniques have been proposed. For few applications, an algorithmic - based fault tolerance (ABFT) system has attempt to abuse the algorithmic properties to identify and adjust mistakes. One example FFT used. There are various protection schemes to identify and adjust errors in FFTs. It is normal to discover various blocks are working in parallel. Recently; a new method is exploiting to implement a blame tolerance in parallel. In this work, same method is first applicable to parallel FFT and then secured methods are merged that the use of error correction codes (ECCs) and parseval checks are used to detect and correct a single bit fault. Trellis code is applied to parallel FFTs to protect the errors which are used to detect and correct a multibit faults are proposed and evaluated. The 4-point FFT is protected with the input32-bit length .Simulation and Synthesis report for FFT using ECC,SOS,ECC-SOS,Trellis codes are obtained in Xilinx software14.2v.Area,power,delay is analyzed in cadence using 90nm & 180nmTechnology.