Design Systems for VLSI Circuits
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18

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6

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Published By Springer Netherlands

9789024735624, 9789400936492

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Verification Algorithms for VLSI Synthesis

Design Systems for VLSI Circuits ◽

10.1007/978-94-009-3649-2_7 ◽

1987 ◽

pp. 249-300 ◽

Author(s):

Gary D. Hachtel ◽

Reily M. Jacoby

Keyword(s):

Verification Algorithms

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Abstraction and Layering in Silicon Compilation Tools

Design Systems for VLSI Circuits ◽

10.1007/978-94-009-3649-2_3 ◽

1987 ◽

pp. 39-64 ◽

Author(s):

Howard E. Shrobe

Keyword(s):

Silicon Compilation

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The M E G A System for Semi-Custom Design

Design Systems for VLSI Circuits ◽

10.1007/978-94-009-3649-2_16 ◽

1987 ◽

pp. 527-537 ◽

Author(s):

U. G. Baitinger ◽

H. M. Lipp ◽

D. A. Mlynski ◽

K. Reiss

Keyword(s):

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Automatic Layout of Integrated Circuits

Design Systems for VLSI Circuits ◽

10.1007/978-94-009-3649-2_5 ◽

1987 ◽

pp. 113-195 ◽

Author(s):

Alberto Sangiovanni-Vincentelli

Keyword(s):

Integrated Circuits ◽

Automatic Layout

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Module Generators for VLSI Design

Design Systems for VLSI Circuits ◽

10.1007/978-94-009-3649-2_2 ◽

1987 ◽

pp. 17-38

Author(s):

Jonathan Allen

Keyword(s):

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The Socrates Logic Synthesis and Optimization System

Design Systems for VLSI Circuits ◽

10.1007/978-94-009-3649-2_14 ◽

1987 ◽

pp. 473-498 ◽

Author(s):

Aart J. Geus ◽

David J. Gregory

Keyword(s):

Logic Synthesis ◽

Optimization System

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Layout Compilation

Design Systems for VLSI Circuits ◽

10.1007/978-94-009-3649-2_13 ◽

1987 ◽

pp. 439-472 ◽

Author(s):

Ralph Otten

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Design of Module Generators and Silicon Compilers

Design Systems for VLSI Circuits ◽

10.1007/978-94-009-3649-2_12 ◽

1987 ◽

pp. 403-437 ◽

Author(s):

Misha R. Burich

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Algorithms for Multi-Level Logic Synthesis and Optimization

Design Systems for VLSI Circuits ◽

10.1007/978-94-009-3649-2_6 ◽

1987 ◽

pp. 197-248 ◽

Author(s):

R. K. Brayton

Keyword(s):

Logic Synthesis ◽

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Logic Synthesis

Design Systems for VLSI Circuits ◽

10.1007/978-94-009-3649-2_8 ◽

1987 ◽

pp. 301-326 ◽

Author(s):

Daniel Brand

Keyword(s):

Logic Synthesis

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