Verification Algorithms for VLSI Synthesis

1987 ◽  
pp. 249-300 ◽  
Author(s):  
Gary D. Hachtel ◽  
Reily M. Jacoby
Keyword(s):  
Verification Algorithms

Efficient Symbolic Representations for Arithmetic Constraints in Verification

2003 ◽  
Vol 14 (04) ◽  
pp. 605-624 ◽  
Author(s):  
Constantinos Bartzis ◽  
Tevfik Bultan
Keyword(s):  
Finite Automata ◽  
Transition Function ◽  
Linear Constraints ◽  
Symbolic Representations ◽  
Integer Variables ◽  
Efficient Storage ◽  
Verification Algorithms ◽  
Infinite State Systems ◽  
Construction Algorithms ◽  
Infinite State

In this paper we discuss efficient symbolic representations for infinite-state systems specified using linear arithmetic constraints. We give algorithms for constructing finite automata which represent integer sets that satisfy linear constraints. These automata can represent either signed or unsigned integers and have a lower number of states compared to other similar approaches. We present efficient storage techniques for the transition function of the automata and extend the construction algorithms to formulas on both boolean and integer variables. We also derive conditions which guarantee that the pre-condition computations used in symbolic verification algorithms do not cause an exponential increase in the automata size. We experimentally compare different symbolic representations by using them to verify non-trivial concurrent systems. Experimental results show that the symbolic representations based on our construction algorithms outperform the polyhedral representation used in Omega Library, and the automata representation used in LASH.

MODELING AND VERIFYING COMPOSITE DYNAMIC EVOLUTION OF SOFTWARE ARCHITECTURES USING HYPERGRAPH GRAMMARS

2013 ◽  
Vol 23 (06) ◽  
pp. 775-799 ◽  
Author(s):  
HONGZHEN XU ◽  
GUOSUN ZENG
Keyword(s):  
Data Structures ◽  
Formal Method ◽  
Graphical Representation ◽  
General Structure ◽  
Software Systems ◽  
Dynamic Evolution ◽  
Software Architectures ◽  
Model Composite ◽  
Verification Algorithms ◽  
Data Structures And Algorithms

As software systems become more and more complex, there is need to consider not only data structures and algorithms but also the general structure or architecture of the system. Many researchers have presently focused on dynamic evolution of software architectures. Most of them usually emphasized on describing and analyzing the dynamic evolution process of software architectures, while lacking formally modeling and verifying composite dynamic evolution of software architectures. In this paper, we propose a formal method of modeling and verifying composite dynamic evolution of software architectures using hypergraph grammars. We represent software architectures with hypergraphs, give out corresponding composite evolution rules of software architectures, and then model composite dynamic evolution of software architectures according to those rules. At last we verify the liveness property of composite dynamic evolution of software architectures using model checking, and give out corresponding verification algorithms. Our approach provides a graphical representation for composite dynamic evolution of software architectures, and displays a formal theoretical basis on grammars.

Survey of the current voter verification algorithms

2008 ◽  
Author(s):  
Majid Javid Moayed ◽  
Abdul Azim Abdul Ghani ◽  
Ramlan Mahmod
Keyword(s):  
Verification Algorithms

scholarly journals Transforming Undecidable Synthesis Problems into Decidable Problems

10.29007/tj84 ◽  
2018 ◽  
Author(s):  
Bernd Finkbeiner
Keyword(s):  
Distributed Systems ◽  
Formal Specification ◽  
Synthesis Problem ◽  
Specific System ◽  
System Architectures ◽  
Development Stages ◽  
Verification Algorithms ◽  
Local Specifications ◽  
Full Design ◽  
Uniform Treatment

Synthesis holds the promise to revolutionize the development ofcomplex systems by automating the translation from specifications toimplementations. Synthesis algorithms are based on the same level ofmathematical rigor as verification algorithms but can be applied atearlier development stages, when only parts of the design areavailable. Given a formal specification of the desired systemproperties, for example in a temporal logic, we determine if thepartial design can be completed into a full design that satisfies theproperties.For general distributed systems, the synthesis problem is undecidable.However, there has been a sequence of discoveries where thedecidability was established for specific system architectures, suchas pipelines and rings, or other restrictions on the problem, such aslocal specifications. Encouraged by these findings, new specificationlanguages like Coordination Logic aim for a uniform treatment of thesynthesis problem.In this talk, I will review several techniques that transformundecidable synthesis problems into decidable problems.

Iris Based Human Verification Algorithms

2004 ◽  
pp. 458-466 ◽  
Author(s):  
Bhola Ram Meena ◽  
Mayank Vatsa ◽  
Richa Singh ◽  
Phalguni Gupta
Keyword(s):  
Verification Algorithms

scholarly journals CPU Energy Meter: A Tool for Energy-Aware Algorithms Engineering

2020 ◽  
pp. 126-133 ◽  
Author(s):  
Dirk Beyer ◽  
Philipp Wendler
Keyword(s):  
Energy Consumption ◽  
Data Centers ◽  
Living Environment ◽  
Tool Support ◽  
Energy Aware ◽  
Cpu Time ◽  
Energy Meter ◽  
Efficiency Of Algorithms ◽  
Verification Algorithms ◽  
Computational Processes

Abstract Verification algorithms are among the most resource-intensive computation tasks. Saving energy is important for our living environment and to save cost in data centers. Yet, researchers compare the efficiency of algorithms still in terms of consumption of CPU time (or even wall time). Perhaps one reason for this is that measuring energy consumption of computational processes is not as convenient as measuring the consumed time and there is no sufficient tool support. To close this gap, we contribute CPU Energy Meter, a small tool that takes care of reading the energy values that Intel CPUs track inside the chip. In order to make energy measurements as easy as possible, we integrated CPU Energy Meter into BenchExec, a benchmarking tool that is already used by many researchers and competitions in the domain of formal methods. As evidence for usefulness, we explored the energy consumption of some state-of-the-art verifiers and report some interesting insights, for example, that energy consumption is not necessarily correlated with CPU time.

Sign in / Sign up

Export Citation Format

Share Document