2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Latest Publications

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9781728122601

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High Performance Memory Repair

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2019.8875490 ◽

2019 ◽

Author(s):

Feroze Merchant ◽

Anandraj Devarajan ◽

Anik Basu ◽

Dave Ashen ◽

Brandon Yelton ◽

...

Keyword(s):

High Performance ◽

Memory Repair

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Challenges of Reliability Assessment and Enhancement in Autonomous Systems

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2019.8875379 ◽

2019 ◽

Cited By ~ 1

Author(s):

Maksim Jenihhin ◽

Matteo Sonza Reorda ◽

Aneesh Balakrishnan ◽

Dan Alexandrescu

Keyword(s):

Autonomous Systems ◽

Reliability Assessment

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Understanding of GPU Architectural Vulnerability for Deep Learning Workloads

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2019.8875404 ◽

2019 ◽

Author(s):

Danny Santoso ◽

Hyeran Jeon

Keyword(s):

Deep Learning

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Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2019.8875431 ◽

2019 ◽

Cited By ~ 2

Author(s):

Mahsa Mousavi ◽

Hamid Reza Pourshaghaghi ◽

Henk Corporaal ◽

Akash Kumar

Keyword(s):

Repair Time

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Foreword

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2019.8875332 ◽

2019 ◽

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Developing a Configurable Fault Tolerant Multicore System for Optimized Sensor Processing

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2019.8875433 ◽

2019 ◽

Author(s):

Markus Ulbricht ◽

Rizwan Tariq Syed ◽

Milos Krstic

Keyword(s):

Fault Tolerant ◽

Multicore System ◽

Sensor Processing

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Fault Tolerant Photovoltaic Array: A Repair Circuit Based on Memristor Sensing

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2019.8875467 ◽

2019 ◽

Author(s):

Luca Gnoli ◽

Jimson Mathew ◽

Marco Ottavi ◽

Giuseppe Carnicelli ◽

Alessio Parisi ◽

...

Keyword(s):

Fault Tolerant ◽

Photovoltaic Array

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Parity-Based Concurrent Error Detection Schemes for the ChaCha Stream Cipher

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2019.8875478 ◽

2019 ◽

Author(s):

Alexander Zeh ◽

Manuela Meier ◽

Viola Rieger

Keyword(s):

Error Detection ◽

Stream Cipher ◽

Concurrent Error Detection ◽

Detection Schemes

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Increasing the Efficiency and Efficacy of Selective-Hardening for Parallel Applications

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2019.8875300 ◽

2019 ◽

Author(s):

Daniel Oliveira ◽

Philippe Navaux ◽

Paolo Rech

Keyword(s):

Parallel Applications

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Scalable and Configurable Multi-Chip SRAM in a Package for Space Applications

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2019.8875489 ◽

2019 ◽

Cited By ~ 1

Author(s):

Aleksandar Simevski ◽

Patryk Skoncej ◽

Cristiano Calligaro ◽

Milos Krstic

Keyword(s):

Space Applications

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2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

High Performance Memory Repair

Challenges of Reliability Assessment and Enhancement in Autonomous Systems

Understanding of GPU Architectural Vulnerability for Deep Learning Workloads

Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory

Foreword

Developing a Configurable Fault Tolerant Multicore System for Optimized Sensor Processing

Fault Tolerant Photovoltaic Array: A Repair Circuit Based on Memristor Sensing

Parity-Based Concurrent Error Detection Schemes for the ChaCha Stream Cipher

Increasing the Efficiency and Efficacy of Selective-Hardening for Parallel Applications

Scalable and Configurable Multi-Chip SRAM in a Package for Space Applications

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Latest Publications