Digital Logic Design Using Verilog
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15

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Published By Springer India

9788132227892, 9788132227915

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Complex Designs Using Verilog RTL

Digital Logic Design Using Verilog ◽

10.1007/978-81-322-2791-5_7 ◽

2016 ◽

pp. 171-196

Author(s):

Vaibbhav Taraate

Low Power Design

Digital Logic Design Using Verilog ◽

10.1007/978-81-322-2791-5_14 ◽

2016 ◽

pp. 359-380

Author(s):

Vaibbhav Taraate

Keyword(s):

Low Power ◽

Low Power Design

System on Chip (SOC) Design

Digital Logic Design Using Verilog ◽

10.1007/978-81-322-2791-5_15 ◽

2016 ◽

pp. 381-398

Author(s):

Vaibbhav Taraate

Keyword(s):

System On Chip ◽

On Chip

Sequential Design Guidelines

Digital Logic Design Using Verilog ◽

10.1007/978-81-322-2791-5_6 ◽

2016 ◽

pp. 145-169

Author(s):

Vaibbhav Taraate

Keyword(s):

Design Guidelines ◽

Sequential Design

Static Timing Analysis

Digital Logic Design Using Verilog ◽

10.1007/978-81-322-2791-5_11 ◽

2016 ◽

pp. 277-298

Author(s):

Vaibbhav Taraate

Keyword(s):

Timing Analysis ◽

Static Timing Analysis ◽

Static Timing

Simulation Concepts and PLD-Based Designs

Digital Logic Design Using Verilog ◽

10.1007/978-81-322-2791-5_9 ◽

2016 ◽

pp. 219-253

Author(s):

Vaibbhav Taraate

Constraining ASIC Design

Digital Logic Design Using Verilog ◽

10.1007/978-81-322-2791-5_12 ◽

2016 ◽

pp. 299-320

Author(s):

Vaibbhav Taraate

Keyword(s):

Asic Design

Combinational Logic Design (Part I)

Digital Logic Design Using Verilog ◽

10.1007/978-81-322-2791-5_2 ◽

2016 ◽

pp. 27-52

Author(s):

Vaibbhav Taraate

Keyword(s):

Logic Design ◽

Combinational Logic

Combinational Design Guidelines

Digital Logic Design Using Verilog ◽

10.1007/978-81-322-2791-5_4 ◽

2016 ◽

pp. 79-102

Author(s):

Vaibbhav Taraate

Keyword(s):

Design Guidelines

Introduction

Digital Logic Design Using Verilog ◽

10.1007/978-81-322-2791-5_1 ◽

2016 ◽

pp. 1-26

Author(s):

Vaibbhav Taraate