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Proceedings of the 18th System Level Interconnect Prediction Workshop on ZZZ - SLIP '16
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8
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Published By ACM Press
9781450344302
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Buffered Interconnects in 3D IC Layout Design
Proceedings of the 18th System Level Interconnect Prediction Workshop on ZZZ - SLIP '16
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10.1145/2947357.2947366
◽
2016
◽
Cited By ~ 3
Author(s):
Mohammad A. Ahmed
◽
Sucheta Mohapatra
◽
Malgorzata Chrzanowska-Jeske
Keyword(s):
Layout Design
◽
3D Ic
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A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects
Proceedings of the 18th System Level Interconnect Prediction Workshop on ZZZ - SLIP '16
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10.1145/2947357.2947362
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2016
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Cited By ~ 7
Author(s):
Ishan G. Thakkar
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Sai Vineel Reddy Chittamuru
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Sudeep Pasricha
Keyword(s):
Comparative Analysis
◽
Front End
◽
Silicon Photonic
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On Chip
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Revisiting 3DIC Benefit with Multiple Tiers
Proceedings of the 18th System Level Interconnect Prediction Workshop on ZZZ - SLIP '16
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10.1145/2947357.2947363
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2016
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Cited By ~ 3
Author(s):
Wei-Ting Jonas Chan
◽
Andrew B. Kahng
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Jiajia Li
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A Demand-Aware Predictive Dynamic Bandwidth Allocation Mechanism for Wireless Network-on-Chip
Proceedings of the 18th System Level Interconnect Prediction Workshop on ZZZ - SLIP '16
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10.1145/2947357.2947361
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2016
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Cited By ~ 3
Author(s):
Naseef Mansoor
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Md Shahriar Shamim
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Amlan Ganguly
Keyword(s):
Wireless Network
◽
Bandwidth Allocation
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Network On Chip
◽
Dynamic Bandwidth Allocation
◽
Allocation Mechanism
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On Chip
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Dynamic Bandwidth
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Connectivity Effects on Energy and Area for Neuromorphic System with High Speed Asynchronous Pulse Mode Links
Proceedings of the 18th System Level Interconnect Prediction Workshop on ZZZ - SLIP '16
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10.1145/2947357.2947365
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2016
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Cited By ~ 1
Author(s):
Carrie Segal
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Aditya Dalakoti
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Merritt Miller
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Forrest Brewer
Keyword(s):
High Speed
◽
Pulse Mode
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Neuromorphic System
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Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits
Proceedings of the 18th System Level Interconnect Prediction Workshop on ZZZ - SLIP '16
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10.1145/2947357.2947364
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2016
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Author(s):
Chih-Cheng Hsu
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Mark Po-Hung Lin
◽
Masanori Hashimoto
Keyword(s):
Low Power
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Spin-Hall Assisted STT-RAM Design and Discussion
Proceedings of the 18th System Level Interconnect Prediction Workshop on ZZZ - SLIP '16
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10.1145/2947357.2947360
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2016
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Cited By ~ 2
Author(s):
Enes Eken
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Ismail Bayram
◽
Yaojun Zhang
◽
Bonan Yan
◽
Wenqing Wu
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...
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Topologically-Geometric Routing
Proceedings of the 18th System Level Interconnect Prediction Workshop on ZZZ - SLIP '16
◽
10.1145/2947357.2947367
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2016
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Author(s):
Roman Bazylevych
◽
Marek Pałasiński
◽
Lubov Bazylevych
Keyword(s):
Geometric Routing
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