Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650)
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Published By IEEE Comput. Soc

076950650x

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Producer-consumer pipelining for structured-data in a fine-grain non-strict dataflow language on commodity machines

Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650) ◽

10.1109/iwia.1999.898845 ◽

2003 ◽

Author(s):

K. Inenaga ◽

S. Kusakabe ◽

M. Amamiya

Keyword(s):

Structured Data ◽

Fine Grain

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Evaluation of compiler-assisted software DSM schemes for a workstation cluster

Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650) ◽

10.1109/iwia.1999.898843 ◽

2003 ◽

Author(s):

J. Niwa ◽

T. Inagaki ◽

T. Matsumoto ◽

K. Hiraki

Keyword(s):

Workstation Cluster ◽

Software Dsm

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A heuristic approach to improve a branch and bound based program partitioning algorithm

Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650) ◽

10.1109/iwia.1999.898848 ◽

2003 ◽

Author(s):

M. Takata ◽

Y. Kunieda ◽

K. Joe

Keyword(s):

Branch And Bound ◽

Heuristic Approach ◽

Partitioning Algorithm ◽

Program Partitioning

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Selective guarded execution using profiling on a dynamically scheduled processor

Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650) ◽

10.1109/iwia.1999.898839 ◽

2003 ◽

Author(s):

S. Mantripragada ◽

A. Nicolau

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PIM architectures to support petaflops level computation in the HTMT machine

Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650) ◽

10.1109/iwia.1999.898841 ◽

2003 ◽

Cited By ~ 8

Author(s):

P.M. Kogge ◽

J.b. Brockman ◽

V.W. Freeh

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Near fine grain parallel processing using static scheduling on single chip multiprocessors

Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650) ◽

10.1109/iwia.1999.898840 ◽

2003 ◽

Cited By ~ 3

Author(s):

K. Kimura ◽

H. Kasahara

Keyword(s):

Parallel Processing ◽

Chip Multiprocessors ◽

Single Chip ◽

Static Scheduling ◽

Fine Grain

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SCIMA: a novel architecture for high performance computing

Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650) ◽

10.1109/iwia.1999.898842 ◽

2003 ◽

Author(s):

H. Nakamura ◽

H. Okawara ◽

T. Boku ◽

M. Kondo ◽

S. Sakai

Keyword(s):

High Performance Computing ◽

High Performance ◽

Performance Computing

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Laurasia and Wind: a compiler-controlled software DSM for WS/PC clusters

Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650) ◽

10.1109/iwia.1999.898846 ◽

2003 ◽

Author(s):

T. Uehara ◽

S. Saito ◽

K. Joe ◽

Y. Kunieda

Keyword(s):

Software Dsm

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Improved implementations of the speculative memory access mechanism specMEM

Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650) ◽

10.1109/iwia.1999.898847 ◽

2003 ◽

Author(s):

H. Nakashima ◽

T. Sato ◽

H. Matsuo ◽

K. Ohno

Keyword(s):

Memory Access

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On the parallelization of electrodynamic multilevel fast multipole method on distributed memory computers

Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650) ◽

10.1109/iwia.1999.898838 ◽

2003 ◽

Cited By ~ 7

Author(s):

S. Velamparaambil ◽

Jiming Song ◽

Weng Cho Chew

Keyword(s):

Distributed Memory ◽

Fast Multipole Method ◽

Fast Multipole ◽

Multipole Method

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Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Producer-consumer pipelining for structured-data in a fine-grain non-strict dataflow language on commodity machines

Evaluation of compiler-assisted software DSM schemes for a workstation cluster

A heuristic approach to improve a branch and bound based program partitioning algorithm

Selective guarded execution using profiling on a dynamically scheduled processor

PIM architectures to support petaflops level computation in the HTMT machine

Near fine grain parallel processing using static scheduling on single chip multiprocessors

SCIMA: a novel architecture for high performance computing

Laurasia and Wind: a compiler-controlled software DSM for WS/PC clusters

Improved implementations of the speculative memory access mechanism specMEM

On the parallelization of electrodynamic multilevel fast multipole method on distributed memory computers

Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650)
Latest Publications