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2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
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Published By IEEE
9781665415033
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Power/Performance/Area Evaluations for Next-Generation HPC Processors using the A64FX Chip
2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
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10.1109/coolchips52128.2021.9410320
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2021
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Author(s):
Eishi Arima
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Yuetsu Kodama
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Tetsuya Odajima
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Miwako Tsuji
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Mitsuhisa Sato
Keyword(s):
Next Generation
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Power Performance
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Performance Area
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Message from the Program Committee Chairs
2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
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10.1109/coolchips52128.2021.9410315
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2021
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Keyword(s):
Program Committee
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Final Program
2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
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10.1109/coolchips52128.2021.9410348
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2021
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An Energy-Efficient Deep Neural Network Training Processor with Bit-Slice-Level Reconfigurability and Sparsity Exploitation
2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
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10.1109/coolchips52128.2021.9410324
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2021
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Author(s):
Donghyeon Han
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Dongseok Im
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Gwangtae Park
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Youngwoo Kim
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Seokchan Song
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...
Keyword(s):
Neural Network
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Energy Efficient
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Deep Neural Network
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Neural Network Training
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Network Training
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Panel Discussions
2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
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10.1109/coolchips52128.2021.9410310
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2021
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List of the Committees Members
2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
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10.1109/coolchips52128.2021.9410317
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2021
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2021 IEEE COOL Chips 24 Supporting Organization
2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
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10.1109/coolchips52128.2021.9410311
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2021
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Messgae from the Organizing Committee Chair
2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
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10.1109/coolchips52128.2021.9410319
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2021
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Keyword(s):
Committee Chair
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Hybrid Network of Packet Switching and STDM in a Multi-FPGA System
2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
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10.1109/coolchips52128.2021.9410322
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2021
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Author(s):
Tomoki Shimizu
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Kohei Ito
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Kensuke Iizuka
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Kazuei Hironaka
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Hideharu Amano
Keyword(s):
Packet Switching
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Hybrid Network
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A Metadata Prefetching Mechanism for Hybrid Memory Architectures
2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
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10.1109/coolchips52128.2021.9410321
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2021
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Author(s):
Shunsuke Tsukada
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Hikaru Takayashiki
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Masayuki Sato
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Kazuhiko Komatsu
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Hiroaki Kobayashi
Keyword(s):
Hybrid Memory
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Memory Architectures
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