CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures

Reconfigurable architectures are quickly gaining in popularity due to their flexibility and ability to provide high energy efficiency. However, reconfigurable systems allow for a huge design space. Iterative design space exploration (DSE) is often required to achieve good Pareto points with respect to some combination of performance, area, and/or energy. DSE tools depend on information about hardware characteristics in these aspects. These characteristics can be obtained from hardware synthesis and net-list simulation, but this is very time-consuming. Therefore, architecture models are common. This work introduces CGRA-EAM (Coarse-Grained Reconfigurable Architecture - Energy & Area Model), a model for energy and area estimation framework for coarse-grained reconfigurable architectures. The model is evaluated for the Blocks CGRA. The results demonstrate that the mean absolute percentage error is 15.5% and 2.1% for energy and area, respectively, while the model achieves a speedup of close to three orders of magnitude compared to synthesis.

Using Combinations of Both Clinical and Radiographic Parameters to Develop a Diagnostic Prediction Model Demonstrated an Excellent Performance in Early Detection of Patients with Blount’s Disease

Early identification of pathological causes for pediatric genu varum (bowlegs) is crucial for preventing a progressive, irreversible knee deformity of the child. This study aims to develop and validate a diagnostic clinical prediction algorithm for assisting physicians in distinguishing an early stage of Blount’s disease from the physiologic bowlegs to provide an early treatment that could prevent the progressive, irreversible deformity. The diagnostic prediction model for differentiating an early stage of Blount’s disease from the physiologic bowlegs was developed under a retrospective case-control study from 2000 to 2017. Stepwise backward elimination of multivariable logistic regression modeling was used to derive a diagnostic model. A total of 158 limbs from 79 patients were included. Of those, 84 limbs (53.2%) were diagnosed as Blount’s disease. The final model that included age, BMI, MDA, and MMB showed excellent performance (area under the receiver operating characteristic (AuROC) curve: 0.85, 95% confidence interval 0.79 to 0.91) with good calibration. The proposed diagnostic prediction model for discriminating an early stage of Blount’s disease from physiologic bowlegs showed high discriminative ability with minimal optimism.

НАТИВНАЯ ТЕХНОЛОГИЧЕСКАЯ ПЛАТФОРМА ДЛЯ ФИЗИЧЕСКОГО ПРОЕКТИРОВАНИЯ СУБНАНОМЕТРОВЫХ СНК ТЕХНОЛОГИИ 16 НМ И НИЖЕ

Представлен новый подход к физическому проектированию SoC, ориентированный на параметры трассировки (Detailed Routing Centered), включающий элементы физического ресинтеза для оптимизации кристалла и обеспечивающий получение оптимального результата по критерию PPA (Power Performance Area). Такой подход позволяет практически свести к нулю расхождение по оценке задержек после размещения с реальными задержками, полученными после трассировки. Данный подход реализован в платформе Aprisa (произн. «Апрайза») P&R компании Mentor Graphics.

Corticomuscular and Intermuscular Coupling in Simple Hand Movements to Enable a Hybrid Brain–Computer Interface

Hybrid Brain–Computer Interfaces (BCIs) for upper limb rehabilitation after stroke should enable the reinforcement of “more normal” brain and muscular activity. Here, we propose the combination of corticomuscular coherence (CMC) and intermuscular coherence (IMC) as control features for a novel hybrid BCI for rehabilitation purposes. Multiple electroencephalographic (EEG) signals and surface electromyography (EMG) from 5 muscles per side were collected in 20 healthy participants performing finger extension (Ext) and grasping (Grasp) with both dominant and non-dominant hand. Grand average of CMC and IMC patterns showed a bilateral sensorimotor area as well as multiple muscles involvement. CMC and IMC values were used as features to classify each task versus rest and Ext versus Grasp. We demonstrated that a combination of CMC and IMC features allows for classification of both movements versus rest with better performance (Area Under the receiver operating characteristic Curve, AUC) for the Ext movement (0.97) with respect to Grasp (0.88). Classification of Ext versus Grasp also showed high performances (0.99). All in all, these preliminary findings indicate that the combination of CMC and IMC could provide for a comprehensive framework for simple hand movements to eventually be employed in a hybrid BCI system for post-stroke rehabilitation.

Device Quantization Policy and Power-Performance- Area Co-Optimization Strategy in Variation-Aware In-memory Computing Design

Device quantization of in-memory computing (IMC) that considers the non-negligible variation and finite dynamic range of practical memory technology is investigated, aiming for quantitatively co-optimizing system performance on accuracy, power, and area. Architecture- and algorithm-level solutions are taken into consideration. Weight-separate mapping, VGG-like algorithm, multiple cells per weight, and fine-tuning of the classifier layer are effective for suppressing inference accuracy loss due to variation and allow for the lowest possible weight precision to improve area and energy efficiency. Higher priority should be given to developing low-conductance and low-variability memory devices that are essential for energy and area-efficiency IMC whereas low bit precision (< 3b) and memory window (<10) are less concerned.

A Study of Non Performing Advances and It’s Management With Special Reference to Punjab National Bank

Banking industry plays an important role in the development of an economy. Banks have become very cautious in extending loans. The reason being mounting non-performing assets (NPAs). NPAs put negative impact on the profitability, capital adequacy ratio and credibility of banks. It is defined as a loan asset, which has ceased to generate any income for a bank whether in the form of interest or principal repayment. As per the prudential norms suggested by the Reserve Bank of India (RBI), a bank cannot book interest on an NPA on accrual basis. In other words, such interests can be booked only when it has been actually received. Therefore, this has become what is called as a ‘critical performance area’ of the banking sector as the level of NPAs affects the profitability of a bank. This paper touches upon the meaning and consequently the definition of a non-Performing asset, the conceptual framework of non-performing assets, classification of loan assets and provisions. The study also evaluates the adverse effect of non-performing assets on the return on total assets of Punjab National Bank Limited for the period 2013 to 2015, 2016-17, and 2019-20. Particularly discussing some remedial measures taken up by the Bank to overcome this situation of NPA.

Rapid And Efficient Multi Objective Design Space Exploration Methods In High Level Synthesis Of Computation Intensive Applications

Design Space Exploration (DSE) is an indispensable segment of the High Level Synthesis (HLS) design process. Moreover, the enormous increase in complexity of the recent Very Large Scale Integration (VLSI) circuits has only been possible due to use of advan ced DSE techniquesduring HLS process. This dissertation presents four automated optimization algorithms and methodologies that are capable to handle various multi-objective problems during design space exploration and high level synthesis of computation intensive applications. Algorithmic solutions to four different branches of DSE problems have been proposed in this dissertation viz. a) Solution to power-performance-area/cost trade-off of Digital Signal Processing (DSP) kernels using priority factor process which also includes deriving analytical mathematical model for modern performance parametric frameworks b) Solution to area-performance-power tradeoff/ power-performance-area tradeoff of DSP kernels using hybridization of fuzzy algorithm and vector design space technique with Self-Correction Scheme c) Solution to dual parametric optimization using efficient multi structure genetic algorithm for integrated scheduling and allocation and d) Solution to control step bound static power optimization using power gradient methodology for integrated scheduling and allocation. Some techniques proposed are equipped with pipelined execution time parameter (based on need), in addition to hardware area, power and cost depending on the user’s objective for exploration of a final solution in a short time. In addition to architecture exploration capability, rapid automated circuit generation of DSP kernels is also possible in a short time for verification and synthesis in Field Programmable Gate Array (FPGA) platforms. The proposed exploration approaches are applied to custom data intensive applications application specific processors/custom processors) or standalone Application Specific Integrated Circuits (ASIC’s). Results of the experiments for proposed approaches on all the standard DSP benchmarks have indicated improvements either in terms of exploration runtime, quality of final solution, reduced execution time, power and area or a multiple combination of all factors when compared to recent approaches.

Rapid And Efficient Multi Objective Design Space Exploration Methods In High Level Synthesis Of Computation Intensive Applications

Design Space Exploration (DSE) is an indispensable segment of the High Level Synthesis (HLS) design process. Moreover, the enormous increase in complexity of the recent Very Large Scale Integration (VLSI) circuits has only been possible due to use of advan ced DSE techniquesduring HLS process. This dissertation presents four automated optimization algorithms and methodologies that are capable to handle various multi-objective problems during design space exploration and high level synthesis of computation intensive applications. Algorithmic solutions to four different branches of DSE problems have been proposed in this dissertation viz. a) Solution to power-performance-area/cost trade-off of Digital Signal Processing (DSP) kernels using priority factor process which also includes deriving analytical mathematical model for modern performance parametric frameworks b) Solution to area-performance-power tradeoff/ power-performance-area tradeoff of DSP kernels using hybridization of fuzzy algorithm and vector design space technique with Self-Correction Scheme c) Solution to dual parametric optimization using efficient multi structure genetic algorithm for integrated scheduling and allocation and d) Solution to control step bound static power optimization using power gradient methodology for integrated scheduling and allocation. Some techniques proposed are equipped with pipelined execution time parameter (based on need), in addition to hardware area, power and cost depending on the user’s objective for exploration of a final solution in a short time. In addition to architecture exploration capability, rapid automated circuit generation of DSP kernels is also possible in a short time for verification and synthesis in Field Programmable Gate Array (FPGA) platforms. The proposed exploration approaches are applied to custom data intensive applications application specific processors/custom processors) or standalone Application Specific Integrated Circuits (ASIC’s). Results of the experiments for proposed approaches on all the standard DSP benchmarks have indicated improvements either in terms of exploration runtime, quality of final solution, reduced execution time, power and area or a multiple combination of all factors when compared to recent approaches.