Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06

Multi-processor system design with ESPAM

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06 ◽

10.1145/1176254.1176306 ◽

2006 ◽

Cited By ~ 35

Author(s):

Hristo Nikolov ◽

Todor Stefanov ◽

Ed Deprettere

Keyword(s):

System Design

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System-level power-performance trade-offs in bus matrix communication architecture synthesis

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06 ◽

10.1145/1176254.1176327 ◽

2006 ◽

Cited By ~ 21

Author(s):

Sudeep Pasricha ◽

Young-Hwan Park ◽

Fadi J. Kurdahi ◽

Nikil Dutt

Keyword(s):

System Level ◽

Power Performance ◽

Communication Architecture ◽

Trade Offs

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Automatic phase detection for stochastic on-chip traffic generation

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06 ◽

10.1145/1176254.1176277 ◽

2006 ◽

Cited By ~ 13

Author(s):

Antoine Scherrer ◽

Antoine Fraboulet ◽

Tanguy Risset

Keyword(s):

Phase Detection ◽

Automatic Phase ◽

Traffic Generation ◽

On Chip

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Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06 ◽

10.1145/1176254.1176280 ◽

2006 ◽

Cited By ~ 17

Author(s):

Roshan G. Ragel ◽

Sri Parameswaran

Keyword(s):

Control Flow ◽

Embedded Processors ◽

Control Flow Checking ◽

Improve Reliability

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A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06 ◽

10.1145/1176254.1176287 ◽

2006 ◽

Cited By ~ 39

Author(s):

Martijn Coenen ◽

Srinivasan Murali ◽

Andrei Ruadulescu ◽

Kees Goossens ◽

Giovanni De Micheli

Keyword(s):

Flow Control ◽

Networks On Chip ◽

Buffer Sizing ◽

End To End ◽

On Chip

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Integrated analysis of communicating tasks in MPSoCs

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06 ◽

10.1145/1176254.1176325 ◽

2006 ◽

Cited By ~ 11

Author(s):

Simon Schliecker ◽

Matthias Ivers ◽

Rolf Ernst

Keyword(s):

Integrated Analysis

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A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06 ◽

10.1145/1176254.1176302 ◽

2006 ◽

Cited By ~ 20

Author(s):

Wei Qin ◽

Joseph D'Errico ◽

Xinping Zhu

Keyword(s):

Instruction Set

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Layout aware design of mesh based NoC architectures

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06 ◽

10.1145/1176254.1176288 ◽

2006 ◽

Cited By ~ 11

Author(s):

Krishnan Srinivasan ◽

Karam S. Chatha

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Accurate yet fast modeling of real-time communication

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06 ◽

10.1145/1176254.1176273 ◽

2006 ◽

Cited By ~ 5

Author(s):

Gunar Schirner ◽

Rainer Dömer

Keyword(s):

Real Time

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Fuzzy decision making in embedded system design

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06 ◽

10.1145/1176254.1176309 ◽

2006 ◽

Cited By ~ 11

Author(s):

Alessandro G. Di Nuovo ◽

Maurizio Palesi ◽

Davide Patti ◽

Giuseppe Ascia ◽

Vincenzo Catania

Keyword(s):

Decision Making ◽

Embedded System ◽

System Design ◽

Fuzzy Decision Making ◽

Fuzzy Decision ◽

Embedded System Design

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Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Multi-processor system design with ESPAM

System-level power-performance trade-offs in bus matrix communication architecture synthesis

Automatic phase detection for stochastic on-chip traffic generation

Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability

A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control

Integrated analysis of communicating tasks in MPSoCs

A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation

Layout aware design of mesh based NoC architectures

Accurate yet fast modeling of real-time communication

Fuzzy decision making in embedded system design

Export Citation Format

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By ACM Press

Multi-processor system design with ESPAM

System-level power-performance trade-offs in bus matrix communication architecture synthesis

Automatic phase detection for stochastic on-chip traffic generation

Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability

A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control

Integrated analysis of communicating tasks in MPSoCs

A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation

Layout aware design of mesh based NoC architectures

Accurate yet fast modeling of real-time communication

Fuzzy decision making in embedded system design

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06
Latest Publications