System-level power-performance trade-offs in bus matrix communication architecture synthesis

2006 ◽  
Author(s):  
Sudeep Pasricha ◽  
Young-Hwan Park ◽  
Fadi J. Kurdahi ◽  
Nikil Dutt
Keyword(s):  
System Level ◽  
Power Performance ◽  
Communication Architecture ◽  
Trade Offs

System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory

2002 ◽  
Author(s):  
Kiran Puttaswamy ◽  
Kyu-Won Choi ◽  
Jun Cheol Park ◽  
Vincent J. Mooney ◽  
Abhijit Chatterjee ◽  
...  
Keyword(s):  
Embedded Systems ◽  
System Level ◽  
Power Performance ◽  
Frequency Scaling ◽  
Trade Offs

Power Performance Trade- Offs in Design of SoCs

2004 ◽  
pp. 27-1-27-14
Author(s):  
Victor Zyuban ◽  
Philip Strenski
Keyword(s):  
Power Performance ◽  
Trade Offs

Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes

2003 ◽  
pp. 113-126 ◽  
Author(s):  
Miquel Pericás ◽  
Eduard Ayguadé ◽  
Javier Zalamea ◽  
Josep Llosa ◽  
Mateo Valero
Keyword(s):  
Power Performance ◽  
Trade Offs

System-Level and Architectural Trade-offs

2011 ◽  
pp. 19-43
Author(s):  
Emanuele Lopelli ◽  
Johan van der Tang ◽  
Arthur van Roermund
Keyword(s):  
System Level ◽  
Trade Offs

Packaging without the Package - A More Holistic Moore's Law

2017 ◽  
Vol 2017 (S1) ◽  
pp. 1-40
Author(s):  
Subramanian S. Iyer (Subu)
Keyword(s):  
System Integration ◽  
System Level ◽  
Heterogeneous Integration ◽  
Power Performance ◽  
Wafer Level ◽  
Innovative Materials ◽  
Barrier To Entry ◽  
On Chip ◽  
Market Consolidation ◽  
Conventional Systems

Silicon features have scaled by over 1500X for over six decades, and with the adoption of innovative materials delivered better power-performance, density and till recently, cost per function, almost every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. However, as SoCs have become bigger and more complex, the Non-Recurring Engineering (NRE) Charge and time to market have both ballooned out of control leading to ever increasing market consolidation. We need to address this problem through novel methods of system Integration. With the well-documented slowing down of scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging itself is undergoing a transformation that focuses on overall system performance through integration rather than on packaging individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. More importantly it will allow us to re-architect systems in a very significant way. This transformation is already under way with 3-D stacking of dies, Wafer level fan-out processing, and will evolve to make heterogeneous integration the backbone of a new SoC methodology, extending to integrate entire Systems on Wafers (SoWs). We will describe the technology we use and the results to-date. This has implications in redefining the memory hierarchy in conventional systems and in neuromorphic systems. We extend these concepts to flexible and biocompatible electronics.

scholarly journals Rapid design of aircraft fuel quantity indication systems via multi-objective evolutionary algorithms

2020 ◽  
pp. 1-18
Author(s):  
David Judt ◽  
Craig Lawson ◽  
Albert S.J. van Heerden
Keyword(s):  
System Level ◽  
Fluid Systems ◽  
Trade Offs ◽  
Aircraft Fuel ◽  
Definition Of ◽  
Tank Geometry ◽  
Probe Set ◽  
Accuracy Constraints ◽  
Good Agreement

The design of electrical, mechanical and fluid systems on aircraft is becoming increasingly integrated with the aircraft structure definition process. An example is the aircraft fuel quantity indication (FQI) system, of which the design is strongly dependent on the tank geometry definition. Flexible FQI design methods are therefore desirable to swiftly assess system-level impact due to aircraft level changes. For this purpose, a genetic algorithm with a two-stage fitness assignment and FQI specific crossover procedure is proposed (FQI-GA). It can handle multiple measurement accuracy constraints, is coupled to a parametric definition of the wing tank geometry and is tested with two performance objectives. A range of crossover procedures of comparable node placement problems were tested for FQI-GA. Results show that the combinatorial nature of the probe architecture and accuracy constraints require a probe set selection mechanism before any crossover process. A case study, using approximated Airbus A320 requirements and tank geometry, is conducted and shows good agreement with the probe position results obtained with the FQI-GA. For the objectives of accessibility and probe mass, the Pareto front is linear, with little variation in mass. The case study confirms that the FQI-GA method can incorporate complex requirements and that designers can employ it to swiftly investigate FQI probe layouts and trade-offs.

Sign in / Sign up

Export Citation Format

Share Document