Proceedings of ASP-DAC 95/CHDL 95/VLSI 95 with EDA Technofair ASPDAC-95
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Finding best cones from random clusters for FPGA package partitioning

Proceedings of ASP-DAC 95/CHDL 95/VLSI 95 with EDA Technofair ASPDAC-95 ◽

10.1109/aspdac.1995.486405 ◽

2002 ◽

Author(s):

D. Brasen ◽

J.P. Hiol ◽

G. Saucier

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An intelligent, self-deducing graphical register transfer interface based on a distributed constraint logic computation

Proceedings of ASP-DAC 95/CHDL 95/VLSI 95 with EDA Technofair ASPDAC-95 ◽

10.1109/aspdac.1995.486373 ◽

2002 ◽

Author(s):

G. Jennings

Keyword(s):

Register Transfer ◽

Logic Computation

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Flexible optimization of fixed polarity Reed-Muller expansions for multiple output completely and incompletely specified Boolean functions

Proceedings of ASP-DAC 95/CHDL 95/VLSI 95 with EDA Technofair ASPDAC-95 ◽

10.1109/aspdac.1995.486242 ◽

2002 ◽

Author(s):

Chip-Hong Chang ◽

B.J. Falkowski

Keyword(s):

Boolean Functions

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BIST with negligible aliasing through random cover circuits

Proceedings of ASP-DAC 95/CHDL 95/VLSI 95 with EDA Technofair ASPDAC-95 ◽

10.1109/aspdac.1995.486227 ◽

2002 ◽

Author(s):

T. Bogue ◽

H. Jurgensen ◽

M. Gossel

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Search space reduction in high level synthesis by use of an initial circuit

Proceedings of ASP-DAC 95/CHDL 95/VLSI 95 with EDA Technofair ASPDAC-95 ◽

10.1109/aspdac.1995.486358 ◽

2002 ◽

Author(s):

A. Masuda ◽

H. Imai ◽

J.P. Hansen ◽

M. Sekine

Keyword(s):

Search Space ◽

High Level Synthesis ◽

Space Reduction ◽

Search Space Reduction ◽

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EDIF Version 350/400 and information modelling

Proceedings of ASP-DAC 95/CHDL 95/VLSI 95 with EDA Technofair ASPDAC-95 ◽

10.1109/aspdac.1995.486354 ◽

2002 ◽

Author(s):

H.J. Kahn

Keyword(s):

Information Modelling

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Synthesis and simulation of digital demodulator for infrared data communication

Proceedings of ASP-DAC 95/CHDL 95/VLSI 95 with EDA Technofair ASPDAC-95 ◽

10.1109/aspdac.1995.486349 ◽

2002 ◽

Author(s):

H. Uno ◽

K. Kumatani ◽

I. Shirakawa ◽

T. Chiba

Keyword(s):

Data Communication ◽

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Exploiting signal flow and logic dependency in standard cell placement

Proceedings of ASP-DAC 95/CHDL 95/VLSI 95 with EDA Technofair ASPDAC-95 ◽

10.1109/aspdac.1995.486251 ◽

2002 ◽

Author(s):

J. Cong ◽

D. Xu

Keyword(s):

Standard Cell ◽

Signal Flow ◽

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Description and verification of RTL designs using multiway decision graphs

Proceedings of ASP-DAC 95/CHDL 95/VLSI 95 with EDA Technofair ASPDAC-95 ◽

10.1109/aspdac.1995.486372 ◽

2002 ◽

Author(s):

Zijian Zhou ◽

Xiaoyn Song ◽

F. Corella ◽

E. Cerny ◽

M. Langevin

Keyword(s):

Multiway Decision Graphs

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A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems

Proceedings of ASP-DAC 95/CHDL 95/VLSI 95 with EDA Technofair ASPDAC-95 ◽

10.1109/aspdac.1995.486204 ◽

2002 ◽

Author(s):

C.-J. Shi ◽

J.A. Brzozowski

Keyword(s):

Optimization Problems ◽

Design Of Algorithms ◽

Analysis And Design ◽

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