IEE Proceedings E (Computers and Digital Techniques)
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Published By Institution Of Electrical Engineers

2053-7948
Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Three-layer router for channels with constrained terminals

1993 ◽  
Vol 140 (6) ◽  
pp. 333-340 ◽  
Author(s):  
R.J. Detry ◽  
A.P. Jayasumana

Fault effects in asynchronous sequential logic circuits

1993 ◽  
Vol 140 (6) ◽  
pp. 327-332
Author(s):  
M.-D. Shieh ◽  
C.-L. Wey ◽  
P.D. Fisher
Keyword(s):  
Logic Circuits ◽  
Sequential Logic

Trade-offs in developing fault tolerant software

1993 ◽  
Vol 140 (6) ◽  
pp. 320-326 ◽  
Author(s):  
N.H. Vaidya ◽  
A.D. Singh ◽  
C.M. Krishna
Keyword(s):  
Fault Tolerant ◽  
Trade Offs

Testing check bits at no cost in RAMs with on-chip ECC

1993 ◽  
Vol 140 (6) ◽  
pp. 304-312
Author(s):  
P. Ramanathan ◽  
K.K. Saluja ◽  
M. Franklin
Keyword(s):  
On Chip

Cellular logic bus arbitration

1993 ◽  
Vol 140 (6) ◽  
pp. 289-296
Author(s):  
E.D. Adamides ◽  
P. Iliades ◽  
I. Argyrakis ◽  
Ph. Tsalides ◽  
A. Thanailakis
Keyword(s):  
Bus Arbitration ◽  
Cellular Logic

Synthesis for Reed-Muller directed acyclic graph network

1993 ◽  
Vol 140 (6) ◽  
pp. 357-360
Author(s):  
H. Wu ◽  
N. Zhuang ◽  
M.A. Perkowski
Keyword(s):  
Directed Acyclic Graph ◽  
Acyclic Graph

Two-level logic circuits using EXOR sums of products

1993 ◽  
Vol 140 (6) ◽  
pp. 348-356 ◽  
Author(s):  
J. Saul ◽  
B. Eschermann ◽  
J. Froessl
Keyword(s):  
Logic Circuits ◽  
Sums Of Products

Strongly fault-secure designs for arithmetic arrays

1993 ◽  
Vol 140 (6) ◽  
pp. 341-347
Author(s):  
J.M. Tahir ◽  
S.S. Dlay ◽  
R.N. Gorgui-Naguib ◽  
O.R. Hinton
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