A Very Low Reference Spur Phase Offset Technique in Fractional-N Charge pump PLLs

Fractional-N charge pump phase locked loops (PLLs) suffer from the problem of increased in-band phase noise due to charge pump non-linearity caused by UP/DN chargepump current mismatch. Existing techniques that resolve this problem by introducing phase offset between reference and divide signals cause large reference spurs or increase jitter at PLL output. A very low reference spur phase offset technique is proposed in this work. It produces the lowest reference spurs compared to previously published works. A detailed comparison of the reference spurs caused by the different techniques to introduce phase offset is presented. Simulation results show that the reference spur level generated at the PLL output after applying the proposed technique is 26 dB lower than the existing techniques in the presence of 5% chargepump current mismatch.<br>

A Very Low Reference Spur Phase Offset Technique in Fractional-N Charge pump PLLs

Fractional-N charge pump phase locked loops (PLLs) suffer from the problem of increased in-band phase noise due to charge pump non-linearity caused by UP/DN chargepump current mismatch. Existing techniques that resolve this problem by introducing phase offset between reference and divide signals cause large reference spurs or increase jitter at PLL output. A very low reference spur phase offset technique is proposed in this work. It produces the lowest reference spurs compared to previously published works. A detailed comparison of the reference spurs caused by the different techniques to introduce phase offset is presented. Simulation results show that the reference spur level generated at the PLL output after applying the proposed technique is 26 dB lower than the existing techniques in the presence of 5% chargepump current mismatch.<br>

Reference Spur Reduction in Sampled-loop filter PLLs by Oversampling

<div><div><div><p>A technique to completely eliminate reference spurs in both Integer-N and Fractional-N charge pump phase locked loops (PLLs) based on an oversampled loop filter architecture is proposed. A rigorous analysis of the performance of the proposed technique in the presence of implementation non-idealities is also presented. It is shown through analysis and simulations that the proposed technique, in addition to completely eliminating reference spurs, adds an insignificant area and power overhead when applied to Integer-N PLLs and less than 6% increase in area and power in case of Fractional-N PLLs.</p></div></div></div>

Reference Spur Reduction in Sampled-loop filter PLLs by Oversampling

<div><div><div><p>A technique to completely eliminate reference spurs in both Integer-N and Fractional-N charge pump phase locked loops (PLLs) based on an oversampled loop filter architecture is proposed. A rigorous analysis of the performance of the proposed technique in the presence of implementation non-idealities is also presented. It is shown through analysis and simulations that the proposed technique, in addition to completely eliminating reference spurs, adds an insignificant area and power overhead when applied to Integer-N PLLs and less than 6% increase in area and power in case of Fractional-N PLLs.</p></div></div></div>