2006 IEEE Electrical Performane of Electronic Packaging
Latest Publications

TOTAL DOCUMENTS

100

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

1424406684

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Dielectric Constant and Loss Tangent Characterization of Thin High-K Dielectrics Using Corner-to-Corner Plane Probing

2006 IEEE Electrical Performane of Electronic Packaging ◽

10.1109/epep.2006.321182 ◽

2006 ◽

Cited By ~ 4

Author(s):

A. Ege Engin ◽

Abdemanaf Tambawala ◽

Madhavan Swaminathan ◽

Swapan Bhattacharya ◽

Pranabes Pramanik ◽

...

Keyword(s):

Dielectric Constant ◽

Loss Tangent ◽

Dielectric Constant And Loss ◽

High K

Frequency-Domain Finite Element Electrodynamic Modeling of Lossy Interconnects from DC to Multi-GHz Frequencies

2006 IEEE Electrical Performane of Electronic Packaging ◽

10.1109/epep.2006.321165 ◽

2006 ◽

Author(s):

Hong Wu ◽

Aosheng Rong ◽

Andreas Cangellaris

Keyword(s):

Finite Element ◽

Frequency Domain ◽

Electrodynamic Modeling

Transient Signal Distortion in Silicon-Based Interconnects over Thin-Film Metal Ground Layers

2006 IEEE Electrical Performane of Electronic Packaging ◽

10.1109/epep.2006.321213 ◽

2006 ◽

Cited By ~ 1

Author(s):

L. Zhang ◽

J. Song

Keyword(s):

Thin Film ◽

Transient Signal ◽

Signal Distortion ◽

Silicon Based

Multi-Rate Latency insertion Method for the Fast Transient Simulation of Large Networks with Nonlinear iermination

2006 IEEE Electrical Performane of Electronic Packaging ◽

10.1109/epep.2006.321211 ◽

2006 ◽

Cited By ~ 2

Author(s):

Noritake Tsuboi ◽

Hideki Asai

Keyword(s):

Transient Simulation ◽

Large Networks ◽

Insertion Method ◽

Latency Insertion ◽

Fast Transient

Principles for Physical-Based Gridding of Package Structures

2006 IEEE Electrical Performane of Electronic Packaging ◽

10.1109/epep.2006.321166 ◽

2006 ◽

Cited By ~ 1

Author(s):

B. Rubin

Common Mode Return Loss Consideration in Wirebond Packaging for High Speed SerDes Links

2006 IEEE Electrical Performane of Electronic Packaging ◽

10.1109/epep.2006.321243 ◽

2006 ◽

Cited By ~ 1

Author(s):

Nanju Na ◽

Marcel Arseneault ◽

Katsuyuki Yonehara ◽

Haitian Hu ◽

Deborah Zwitter ◽

...

Keyword(s):

High Speed ◽

Return Loss ◽

Common Mode

Model Order Reduction with Load Constraints

2006 IEEE Electrical Performane of Electronic Packaging ◽

10.1109/epep.2006.321226 ◽

2006 ◽

Cited By ~ 1

Author(s):

Min Ma ◽

Roni Khazaka

Keyword(s):

Model Order Reduction ◽

Order Reduction ◽

Model Order

Developing Improved IO Buffer Behavioral Modeling Methodology Based on IBIS

2006 IEEE Electrical Performane of Electronic Packaging ◽

10.1109/epep.2006.321193 ◽

2006 ◽

Cited By ~ 4

Author(s):

Ambrish Varma ◽

Michael Steer ◽

Paul Franzon

Keyword(s):

Behavioral Modeling ◽

Modeling Methodology

Measurement of Via Currents in Printed Circuit Boards Using Inductive Loops

2006 IEEE Electrical Performane of Electronic Packaging ◽

10.1109/epep.2006.321184 ◽

2006 ◽

Cited By ~ 6

Author(s):

James Weaver ◽

Mark Horowitz

Keyword(s):

Printed Circuit Boards ◽

Circuit Boards ◽

Printed Circuit

Increasing Channel Margin of Distorted Serial Systems

2006 IEEE Electrical Performane of Electronic Packaging ◽

10.1109/epep.2006.321179 ◽

2006 ◽

Author(s):

P. Patel ◽

M. Cases ◽

D. de Araujo ◽

D. Brunker ◽

G. Oganessyan ◽

...

2006 IEEE Electrical Performane of Electronic PackagingLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Dielectric Constant and Loss Tangent Characterization of Thin High-K Dielectrics Using Corner-to-Corner Plane Probing

Frequency-Domain Finite Element Electrodynamic Modeling of Lossy Interconnects from DC to Multi-GHz Frequencies

Transient Signal Distortion in Silicon-Based Interconnects over Thin-Film Metal Ground Layers

Multi-Rate Latency insertion Method for the Fast Transient Simulation of Large Networks with Nonlinear iermination

Principles for Physical-Based Gridding of Package Structures

Common Mode Return Loss Consideration in Wirebond Packaging for High Speed SerDes Links

Model Order Reduction with Load Constraints

Developing Improved IO Buffer Behavioral Modeling Methodology Based on IBIS

Measurement of Via Currents in Printed Circuit Boards Using Inductive Loops

Increasing Channel Margin of Distorted Serial Systems

2006 IEEE Electrical Performane of Electronic Packaging
Latest Publications