2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06)

Policy-based Resource Allocation in Hierarchical Virtual Organizations for Global Grids

2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06) ◽

10.1109/sbac-pad.2006.21 ◽

2006 ◽

Cited By ~ 5

Author(s):

Kyong Hoon Kim ◽

Rajkumar Buyya

Keyword(s):

Resource Allocation ◽

Virtual Organizations

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Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption

2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06) ◽

10.1109/sbac-pad.2006.30 ◽

2006 ◽

Author(s):

Abel Silva Filho ◽

Pablo Viana ◽

Edna Barros ◽

Manoel Lima

Keyword(s):

Energy Consumption ◽

Low Energy ◽

Cache Hierarchy ◽

Tuning Mechanism ◽

Low Energy Consumption ◽

Instruction Caches

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32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice

2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06) ◽

10.1109/sbac-pad.2006.5 ◽

2006 ◽

Cited By ~ 2

Author(s):

Mario Donato Marino ◽

O Paulo

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Dual-Thread Speculation: Two Threads in the Machine are Worth Eight in the Bush

2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06) ◽

10.1109/sbac-pad.2006.17 ◽

2006 ◽

Cited By ~ 2

Author(s):

Fredrik Warg ◽

Per Stenstrom

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Combining Source Routing and Dynamic Fault Tolerance

2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06) ◽

10.1109/sbac-pad.2006.12 ◽

2006 ◽

Cited By ~ 2

Author(s):

Frank Sem-jacobsen ◽

Olav Lysne ◽

Tor Skeie

Keyword(s):

Fault Tolerance ◽

Source Routing

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The mDTSVLIW: a Multi-Threaded Trace-based VLIW Architecture

2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06) ◽

10.1109/sbac-pad.2006.28 ◽

2006 ◽

Cited By ~ 1

Author(s):

P. Rounce ◽

A. F. De Souza

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Runtime System Support for Running Applications with Dynamic and Asynchronous Task Parallelism in Software DSM Systems

2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06) ◽

10.1109/sbac-pad.2006.25 ◽

2006 ◽

Cited By ~ 3

Author(s):

Rafael Mendes ◽

Lauro Whately ◽

Maria De Castro ◽

Cristiana Bentes ◽

Claudio Amorim

Keyword(s):

System Support ◽

Runtime System ◽

Task Parallelism ◽

Software Dsm

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Characterizing the Performance of Data Management Systems on Hyper-Threaded Architectures

2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06) ◽

10.1109/sbac-pad.2006.11 ◽

2006 ◽

Cited By ~ 3

Author(s):

Wessam Hassanein ◽

Moustafa Hammad ◽

Layali Rashid

Keyword(s):

Data Management ◽

Management Systems ◽

Data Management Systems

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Data Segmentation Management Infrastructure in a Database Grid

2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06) ◽

10.1109/sbac-pad.2006.15 ◽

2006 ◽

Author(s):

Reinaldo Lourenso ◽

Sergio Takeo Kofuji

Keyword(s):

Data Segmentation

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Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors

2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06) ◽

10.1109/sbac-pad.2006.14 ◽

2006 ◽

Cited By ~ 2

Author(s):

Daniel Jimenez ◽

Gabriel Loh

Keyword(s):

High Performance ◽

Practical Implementation

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2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Policy-based Resource Allocation in Hierarchical Virtual Organizations for Global Grids

Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption

32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice

Dual-Thread Speculation: Two Threads in the Machine are Worth Eight in the Bush

Combining Source Routing and Dynamic Fault Tolerance

The mDTSVLIW: a Multi-Threaded Trace-based VLIW Architecture

Runtime System Support for Running Applications with Dynamic and Asynchronous Task Parallelism in Software DSM Systems

Characterizing the Performance of Data Management Systems on Hyper-Threaded Architectures

Data Segmentation Management Infrastructure in a Database Grid

Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors

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2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Policy-based Resource Allocation in Hierarchical Virtual Organizations for Global Grids

Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption

32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice

Dual-Thread Speculation: Two Threads in the Machine are Worth Eight in the Bush

Combining Source Routing and Dynamic Fault Tolerance

The mDTSVLIW: a Multi-Threaded Trace-based VLIW Architecture

Runtime System Support for Running Applications with Dynamic and Asynchronous Task Parallelism in Software DSM Systems

Characterizing the Performance of Data Management Systems on Hyper-Threaded Architectures

Data Segmentation Management Infrastructure in a Database Grid

Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors

2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06)
Latest Publications