The Kluwer International Series in Engineering and Computer Science - VHDL for Simulation, Synthesis and Formal Proofs of Hardware
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(FIVE YEARS 0)

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Published By Springer US

9781461365822, 9781461535621

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Bi-directional Switches in VHDL using the 46 Value System

The Kluwer International Series in Engineering and Computer Science - VHDL for Simulation, Synthesis and Formal Proofs of Hardware ◽

10.1007/978-1-4615-3562-1_5 ◽

1992 ◽

pp. 63-71

Author(s):

Alec Stanculescu

Keyword(s):

Value System

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Introducing CASCADE control graphs in VHDL

The Kluwer International Series in Engineering and Computer Science - VHDL for Simulation, Synthesis and Formal Proofs of Hardware ◽

10.1007/978-1-4615-3562-1_20 ◽

1992 ◽

pp. 291-307

Author(s):

Claude Le Faou ◽

Jean Mermet

Keyword(s):

Cascade Control

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Developing a Formal Semantic Definition of VHDL

The Kluwer International Series in Engineering and Computer Science - VHDL for Simulation, Synthesis and Formal Proofs of Hardware ◽

10.1007/978-1-4615-3562-1_17 ◽

1992 ◽

pp. 245-256 ◽

Cited By ~ 4

Author(s):

Philip A. Wilsey

Keyword(s):

Formal Semantic ◽

Definition Of ◽

Semantic Definition

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ASIC Design Using Silicon 1076

The Kluwer International Series in Engineering and Computer Science - VHDL for Simulation, Synthesis and Formal Proofs of Hardware ◽

10.1007/978-1-4615-3562-1_10 ◽

1992 ◽

pp. 135-147

Author(s):

Robert A. Cottrell

Keyword(s):

Asic Design

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Delay Calculation and Back Annotation in VHDL Addressing the Requirements of ASIC Design

The Kluwer International Series in Engineering and Computer Science - VHDL for Simulation, Synthesis and Formal Proofs of Hardware ◽

10.1007/978-1-4615-3562-1_7 ◽

1992 ◽

pp. 87-98

Author(s):

Peter Connor ◽

Sanjay Nayak ◽

Joyce Kraley ◽

Victor Berman

Keyword(s):

Asic Design

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Switch-Level Models in Multi-level VHDL Simulations

The Kluwer International Series in Engineering and Computer Science - VHDL for Simulation, Synthesis and Formal Proofs of Hardware ◽

10.1007/978-1-4615-3562-1_4 ◽

1992 ◽

pp. 43-62 ◽

Cited By ~ 1

Author(s):

K. Khordoc ◽

M. Biotteau ◽

E. Cerny

Keyword(s):

Multi Level

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Timing Constraint Checks in VHDL—a comparative study

The Kluwer International Series in Engineering and Computer Science - VHDL for Simulation, Synthesis and Formal Proofs of Hardware ◽

10.1007/978-1-4615-3562-1_2 ◽

1992 ◽

pp. 17-32 ◽

Cited By ~ 4

Author(s):

Fuhong Liu ◽

Adam Pawlak

Keyword(s):

Comparative Study ◽

Timing Constraint

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Formal verification of VHDL descriptions in Boyer-Moore : first results

The Kluwer International Series in Engineering and Computer Science - VHDL for Simulation, Synthesis and Formal Proofs of Hardware ◽

10.1007/978-1-4615-3562-1_16 ◽

1992 ◽

pp. 227-243 ◽

Cited By ~ 2

Author(s):

Dominique Borrione ◽

Laurence Pierre ◽

Ashraf Salem

Keyword(s):

Formal Verification ◽

First Results

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Using Formalized Timing Diagrams in VHDL Simulation

The Kluwer International Series in Engineering and Computer Science - VHDL for Simulation, Synthesis and Formal Proofs of Hardware ◽

10.1007/978-1-4615-3562-1_3 ◽

1992 ◽

pp. 33-42 ◽

Cited By ~ 1

Author(s):

M. Dufresne ◽

K. Khordoc ◽

E. Cerny

Keyword(s):

Timing Diagrams

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Symbolic Computation of Hierarchical and Interconnected FSMS

The Kluwer International Series in Engineering and Computer Science - VHDL for Simulation, Synthesis and Formal Proofs of Hardware ◽

10.1007/978-1-4615-3562-1_13 ◽

1992 ◽

pp. 179-193 ◽

Cited By ~ 1

Author(s):

Alain Debreil ◽

Christian Berthet ◽

Ahmed Jerraya

Keyword(s):

Symbolic Computation

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The Kluwer International Series in Engineering and Computer Science - VHDL for Simulation, Synthesis and Formal Proofs of HardwareLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer US

Bi-directional Switches in VHDL using the 46 Value System

Introducing CASCADE control graphs in VHDL

Developing a Formal Semantic Definition of VHDL

ASIC Design Using Silicon 1076

Delay Calculation and Back Annotation in VHDL Addressing the Requirements of ASIC Design

Switch-Level Models in Multi-level VHDL Simulations

Timing Constraint Checks in VHDL—a comparative study

Formal verification of VHDL descriptions in Boyer-Moore : first results

Using Formalized Timing Diagrams in VHDL Simulation

Symbolic Computation of Hierarchical and Interconnected FSMS

The Kluwer International Series in Engineering and Computer Science - VHDL for Simulation, Synthesis and Formal Proofs of Hardware
Latest Publications