Development of a device for multiplying numbers by means of FPGA

The authors propose the description of the development of a device for multiplying numbers. The device for multiplying numbers on the field-programmable gate array (FPGA) includes two input and one output registers, fifty-six single-digit adders, sixty four logic elements AND, one exclusive OR gate. The main scientific and technical task in developing a device for multiplying numbers is to reduce hardware complexity using single-bit adders and logic elements. Introduction includes description of works of scientists and researchers whose publications are devoted to design and development of multiplier construction methods, multiplier FIR performance improvement by right-shift and addition method on FPGA (field-programmable gate array) basis. The implementation of MAC-block, hardware implementation of binary multiplier on the basis of multi operand adder, multiplier design by right-sliding and addition with control automaton in the FPGA basis is the actual research tasks presented in a number of papers. The description of features of multiplier implementation, high-speed multipliers with variable bit rate, studies of approaches for designing modular multipliers, FPGA image processing using Brown multiplier for performing convolution operation find application in problems of performance and speed. Also, a number of authors describe implementation of conveyorization method, design of dual multiplier, construction method of 8-bit multiplier with reduced delay, 8-bit high-density systolic multiplier arrays on FPGA and development of high-performance 8-bit multiplier using McCMOS technology. A fragment of a developed device for multiplying numbers is presented in the work by the authors. The principle of operation of a device for multiplication is described. The description of connected elements of the device is given. The timing diagrams of operation of a device for multiplication of numbers are presented.

Modeling Battery Connections in the Electronic Lab

The paper deals with the modeling of the processes of charge-discharge of battery assemblies taking into account their degradation. The results of simulating the cyclic operation of battery assemblies in the Electronics Workbench electronic laboratory are presented, possible schemes of inclusion are given, and options for re-switching batteries during operation are considered as well as connecting additional elements to extend the life of the connection. The simulation took into account the presence of one defective battery in the assembly. The operation of the assembly with a defective battery and a reference battery was compared. As a result of the analysis of parallel-serial and serial-parallel battery connections, the first one is considered preferable. For an assembly with a parallel-serial connection, the time parameters of operation remained almost unchanged, but the differences in the voltages of the defective and other batteries changed more than twice as compared with a serial-parallel connection. The changes in charge, voltage and current of assemblies with a degraded battery and a reference battery are analyzed. Timing diagrams are shown for batteries connected in parallel and in series with defective batteries. Power losses in a defective battery are reduced by choosing a parallel-series assembly, while switching a connection from a serial-parallel connection to a parallel-series one does not lead to compensation for the degradation of battery parameters. Changing the switching time intervals in a wide range does not contribute to increasing the capacity of a defective battery. Degradation of battery parameters leads to sharper surges in voltage, charge and current. The additional power recharge of the defective battery maintains the performance of the entire assembly. Recharge can be performed by connecting in parallel a defective additional battery or a capacitor, which is equivalent to replacing a degraded battery with a new one.

Variants of structures of the ship’s electromotive complex with common DC bus-bars

Schematic and algorithmic solutions for the design and construction of ship’s electromotive systems of various purposes are considered. The analysis of the existing structures of electromotive complexes, as well as the types of electrical converters used is carried out. The structure of an electromotive complex based on a transformerless structure with common DC bus-bars is proposed. The main goals of improvement are to increase energy efficiency, reliability and survivability of an electric power plant, and lower weight and size characteristics. The proposed structure of the ship’s electromotive complex allows braking the propellers without using additional braking circuits with the redistribution of energy between the propeller electric machines and the dissipation of braking energy in the working medium - water. An algorithm is proposed and mathematical modeling of braking and reverse modes of a propeller electric installation is carried out. Timing diagrams of changes in torque, rotation speed and power on each of the propellers for the proposed algorithm of braking and reverse of propeller motors are presented. It is shown that the synthesized structure of the electromotive complex makes it possible to reduce the emissions of pollutants into the environment, as well as to save fuel within the range of 10÷15%, depending on the operating modes of the ship in comparison with the existing structures of the electromotive systems.

The Padding of Vein Image Features and Hardware Designs in M-Health Environments

This chapter describes the timing diagrams of padding features and hardware designs of segmentation, controllers, and filters. Further, the authors have described that the hardware design concept of segmentation task can be performed online in a distributed cloud computing m-health environment. The segmentation phase uses two Gaussian filter functions with different sizes of filter masks and standard deviation with a threshold value to make a distinction between veins image patterns and the corresponding backgrounds in the cloud IoT-based m-health environment. In order to design the hardware architecture of the median filter, the superior moving window architecture is used by researchers to accommodate a larger size median filter in the cloud IoT-based m-health environment.

All-optical integrated 2-to-4 decoder and 1-to-4 demultiplexer circuit with enable using SOA based MZI

In this paper, we propose an all-optical integrated 2-to-4 decoder and a 1-to-4 demultiplexer circuit using SOA based MZI (Mach–Zehnder Interferometer) architecture. The proposed device has been applied an enable signal along with two data input signals at the same wavelength. Four output signals from 2-to-4 decoder and 1-to-4 demultiplexer have been attained at the same wavelength. The output timing diagrams of 2-to-4 decoder and 1-to-4 demultiplexer for different input data conditions with clear eye opening patterns confirms the operation of the proposed logic device at 10 Gb/s. Maximum value of extinction ratio, contrast ratio and minimum value of amplitude modulation achieved for the different output waveforms are 12, 9.5 and 0.1 dB respectively. Easy integration with active and passive devices and simple architecture makes this device suitable for all-optical processing.

Implementation of Fpga-based Pseudo-random Words Generator

A hardware implementation of pseudo-random bit generator based on FPGA chips, which use the principle of reconfigurability that allows the modernization of their algorithms and on-line replacement of the internal structure (reconfiguration) in the process of functioning have been considered in the paper. Available DSP blocks embedded into the structure of FPGA chips allow efficient hardware implementation of the pseudorandom bit generator through the implementation of the basic operations of multiplication with accumulation on the gate level. Using CAD ISE 14.02 Foundation and VHDL language three types of pseudo-random bit generators have been implemented on Spartan series chip 6SLX4CSG225-3, for which time and hardware expenses are represented. Using the simulating system ModelSim SE 10.1c, timing diagrams of simulation for these structures have been obtained.

DEVICE FOR GEOPHYSICAL EXPLORATION OF THE EARTH'S CRUST BASED ON A DETONATION GENERATOR

The article describes the principle of operation of the device for geophysical exploration, which is based on the action of detonation waves to a limited area of the earth's surface at a shallow depth (up to 100 m), a block diagram and timing diagrams explaining the principle of the device. KEYWORDS: geophysical exploration, device, block diagram, principle of operation, timing diagram, detonation generator, phase shift, harmonic component of echo signals.